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authorHeiko Stuebner <heiko@sntech.de>2011-09-27 08:44:37 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 19:01:10 +0900
commite3b454f731e73531bc61e144c1890907103f2b19 (patch)
tree8033e8aaa0f59d880db8c3e1132a70b4f148aedd /arch/arm/plat-s3c24xx
parent7301794c87e508f5919a70d109ea8e79562815ff (diff)
downloadop-kernel-dev-e3b454f731e73531bc61e144c1890907103f2b19.zip
op-kernel-dev-e3b454f731e73531bc61e144c1890907103f2b19.tar.gz
ARM: S3C2443: Move i2s clock definitions to common code
S3C2416/S3C2450 use the same clocks for their i2s blocks and can therefore reuse the existing ones. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 59552c0..f630adf 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -205,9 +205,59 @@ static struct clksrc_clk clksrc_clks[] = {
},
};
+static struct clk clk_i2s_ext = {
+ .name = "i2s-ext",
+};
+
+/* i2s_eplldiv
+ *
+ * This clock is the output from the I2S divisor of ESYSCLK, and is separate
+ * from the mux that comes after it (cannot merge into one single clock)
+*/
+
+static struct clksrc_clk clk_i2s_eplldiv = {
+ .clk = {
+ .name = "i2s-eplldiv",
+ .parent = &clk_esysclk.clk,
+ },
+ .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
+};
+
+/* i2s-ref
+ *
+ * i2s bus reference clock, selectable from external, esysclk or epllref
+ *
+ * Note, this used to be two clocks, but was compressed into one.
+*/
+
+static struct clk *clk_i2s_srclist[] = {
+ [0] = &clk_i2s_eplldiv.clk,
+ [1] = &clk_i2s_ext,
+ [2] = &clk_epllref.clk,
+ [3] = &clk_epllref.clk,
+};
+
+static struct clksrc_clk clk_i2s = {
+ .clk = {
+ .name = "i2s-if",
+ .ctrlbit = S3C2443_SCLKCON_I2SCLK,
+ .enable = s3c2443_clkcon_enable_s,
+
+ },
+ .sources = &(struct clksrc_sources) {
+ .sources = clk_i2s_srclist,
+ .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
+ },
+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
+};
static struct clk init_clocks_off[] = {
{
+ .name = "iis",
+ .parent = &clk_p,
+ .enable = s3c2443_clkcon_enable_p,
+ .ctrlbit = S3C2443_PCLKCON_IIS,
+ }, {
.name = "adc",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
@@ -406,6 +456,8 @@ static struct clk *clks[] __initdata = {
};
static struct clksrc_clk *clksrcs[] __initdata = {
+ &clk_i2s_eplldiv,
+ &clk_i2s,
&clk_usb_bus_host,
&clk_epllref,
&clk_esysclk,
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