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| author | Vaibhav Hiremath <hvaibhav@ti.com> | 2012-07-04 03:40:59 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-07-04 03:40:59 -0600 |
| commit | 248b3b3d841b01d0a5a55b746fc7e5e9edbe65e6 (patch) | |
| tree | a3a805f064d974bada367b7b9377a73ed4b8c9cb /arch/arm/plat-omap | |
| parent | 6887a4131da3adaab011613776d865f4bcfb5678 (diff) | |
| download | op-kernel-dev-248b3b3d841b01d0a5a55b746fc7e5e9edbe65e6.zip op-kernel-dev-248b3b3d841b01d0a5a55b746fc7e5e9edbe65e6.tar.gz | |
ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx
In case of AM33xx family of devices (like cpsw) have different sysc
bit field offsets defined,
sysc_type3:
| 3 2 | 1 0 |
| STDBYMODE | IDLEMODE |
So introduce new sysc_type3 in omap_hwmod common data.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap_hwmod.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b71..2c17103 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -41,6 +41,7 @@ struct omap_device; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; +extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; /* * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant @@ -70,6 +71,15 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) +/* + * OCP SYSCONFIG bit shifts/masks TYPE3. + * This is applicable for some IPs present in AM33XX + */ +#define SYSC_TYPE3_SIDLEMODE_SHIFT 0 +#define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT) +#define SYSC_TYPE3_MIDLEMODE_SHIFT 2 +#define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) + /* OCP SYSSTATUS bit shifts/masks */ #define SYSS_RESETDONE_SHIFT 0 #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) |
