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author | Tero Kristo <tero.kristo@nokia.com> | 2008-08-28 13:13:31 +0000 |
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committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-11-11 14:42:25 -0800 |
commit | f2d1185824fd3ed631f3164daeff59d0b4e55d79 (patch) | |
tree | de31dfc36411fa43ae1fe99d1402e67b53ade827 /arch/arm/plat-omap/dma.c | |
parent | 2f5939c3ec9440a9c3a0baf4d0e1b2cc043aad46 (diff) | |
download | op-kernel-dev-f2d1185824fd3ed631f3164daeff59d0b4e55d79.zip op-kernel-dev-f2d1185824fd3ed631f3164daeff59d0b4e55d79.tar.gz |
OMAP: PM: DMA context save/restore for off-mode support
For HS/EMU devices, these additional features are also used:
- DMA interrupt disable routine added
- Added DMA controller reset to DMA context restore
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
-rw-r--r-- | arch/arm/plat-omap/dma.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 3edffde..3105aaa 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -54,6 +54,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; static int enable_1510_mode; +static struct omap_dma_global_context_registers { + u32 dma_irqenable_l0; + u32 dma_ocp_sysconfig; + u32 dma_gcr; +} omap_dma_global_context; + struct omap_dma_lch { int next_lch; int dev_id; @@ -2341,6 +2347,39 @@ void omap_stop_lcd_dma(void) } EXPORT_SYMBOL(omap_stop_lcd_dma); +void omap_dma_global_context_save(void) +{ + omap_dma_global_context.dma_irqenable_l0 = + dma_read(IRQENABLE_L0); + omap_dma_global_context.dma_ocp_sysconfig = + dma_read(OCP_SYSCONFIG); + omap_dma_global_context.dma_gcr = dma_read(GCR); +} + +void omap_dma_global_context_restore(void) +{ + dma_write(0x2, OCP_SYSCONFIG); + while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS)) + ; + dma_write(omap_dma_global_context.dma_gcr, GCR); + dma_write(omap_dma_global_context.dma_ocp_sysconfig, + OCP_SYSCONFIG); + dma_write(omap_dma_global_context.dma_irqenable_l0, + IRQENABLE_L0); +} + +void omap_dma_disable_irq(int lch) +{ + u32 val; + + if (cpu_class_is_omap2()) { + /* Disable interrupts */ + val = dma_read(IRQENABLE_L0); + val &= ~(1 << lch); + dma_write(val, IRQENABLE_L0); + } +} + /*----------------------------------------------------------------------------*/ static int __init omap_init_dma(void) |