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| author | Pawel Moll <pawel.moll@arm.com> | 2011-05-20 14:39:29 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2011-07-07 19:20:52 +0100 |
| commit | 15eb169bfec291faf25b158cfa9842b72f7803ad (patch) | |
| tree | 33d3e8f89114d531c0fe8f8da176b0dcb65bb996 /arch/arm/mm | |
| parent | dc939cd835d0e2d3ff4197d6e2c017d269616d20 (diff) | |
| download | op-kernel-dev-15eb169bfec291faf25b158cfa9842b72f7803ad.zip op-kernel-dev-15eb169bfec291faf25b158cfa9842b72f7803ad.tar.gz | |
ARM: proc: add Cortex-A5 proc info
This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index a759cca..3185da2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -278,6 +278,7 @@ cpu_resume_l1_flags: * It is assumed that: * - cache type register is implemented */ +__v7_ca5mp_setup: __v7_ca9mp_setup: #ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @@ -444,6 +445,16 @@ __v7_setup_stack: .endm /* + * ARM Ltd. Cortex A5 processor. + */ + .type __v7_ca5mp_proc_info, #object +__v7_ca5mp_proc_info: + .long 0x410fc050 + .long 0xff0ffff0 + __v7_proc __v7_ca5mp_setup + .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info + + /* * ARM Ltd. Cortex A9 processor. */ .type __v7_ca9mp_proc_info, #object |
