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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2007-05-17 10:19:23 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-17 10:19:23 +0100
commit516793c61b3db1f60e0b0d0e3c382bcca9ae84fd (patch)
tree1e9a0b8e01ecac7c60c5d0f6b157181ab1132467 /arch/arm/mm
parentc6af66b9fe93990c70aaee53ce3ce7e53a83676a (diff)
downloadop-kernel-dev-516793c61b3db1f60e0b0d0e3c382bcca9ae84fd.zip
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[ARM] ARMv6: add CPU_HAS_ASID configuration
Presently, we check for the minimum ARM architecture that we're building for to determine whether we need ASID support. This is wrong - if we're going to support a range of CPUs which include ARMv6 or higher, we need the ASID. Convert the checks to use a new configuration symbol, and arrange for ARMv6 and higher CPU entries to select it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 15f0284..5f472a8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -351,6 +351,7 @@ config CPU_V6
select CPU_CACHE_V6
select CPU_CACHE_VIPT
select CPU_CP15_MMU
+ select CPU_HAS_ASID
select CPU_COPY_V6 if MMU
select CPU_TLB_V6 if MMU
@@ -376,6 +377,7 @@ config CPU_V7
select CPU_CACHE_V7
select CPU_CACHE_VIPT
select CPU_CP15_MMU
+ select CPU_HAS_ASID
select CPU_COPY_V6 if MMU
select CPU_TLB_V6 if MMU
@@ -498,6 +500,12 @@ config CPU_TLB_V6
endif
+config CPU_HAS_ASID
+ bool
+ help
+ This indicates whether the CPU has the ASID register; used to
+ tag TLB and possibly cache entries.
+
config CPU_CP15
bool
help
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