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authorSaeed Bishara <saeed@marvell.com>2008-07-02 06:06:32 -1100
committerNicolas Pitre <nico@cam.org>2008-07-07 18:38:24 -0400
commit188237e28d7fece0471640ba86f6d8cd164ed085 (patch)
treed96756da27fbe75e602808c2261cad3b70db964e /arch/arm/mm
parent2e1117d307dba8185a72bac94e57f057e70590ca (diff)
downloadop-kernel-dev-188237e28d7fece0471640ba86f6d8cd164ed085.zip
op-kernel-dev-188237e28d7fece0471640ba86f6d8cd164ed085.tar.gz
[ARM] Feroceon: don't disable BPU on boot
On Feroceon platforms that have a branch prediction unit, bit 11 of the cp15 control register controls the BPU. This patch keeps the old value of this bit instead of always clearing it. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-feroceon.S9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 63ca1ea..f2e5884 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -493,14 +493,15 @@ __feroceon_setup:
.size __feroceon_setup, . - __feroceon_setup
/*
- * R
- * .RVI ZFRS BLDP WCAM
- * .011 0001 ..11 0101
+ * B
+ * R P
+ * .RVI UFRS BLDP WCAM
+ * .011 .001 ..11 0101
*
*/
.type feroceon_crval, #object
feroceon_crval:
- crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
+ crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
__INITDATA
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