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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 09:41:01 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 09:41:01 -0700
commitcdd3a354a05b0c33fe33ab11a0fb0838396cad19 (patch)
treeea2c87bbc2dc5865a97e73e201661d69937b45d5 /arch/arm/mm
parent813a95e5b4fa936bbde10ef89188932745dcd7f4 (diff)
parentada2e35defe6c6f0a986ec8147e47726fbd0e7b1 (diff)
downloadop-kernel-dev-cdd3a354a05b0c33fe33ab11a0fb0838396cad19.zip
op-kernel-dev-cdd3a354a05b0c33fe33ab11a0fb0838396cad19.tar.gz
Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc power management changes from Olof Johansson: "Power management changes here are mostly for the omap platform, but also include cpuidle changes for ux500 and suspend/resume code for mmp." * tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after hwmod reset ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database ARM: OMAP4: hwmod_data: Name the common irq for McBSP ports ARM: OMAP4: hwmod data: I2C: add flag for context restore ARM: OMAP3: hwmod_data: Rename the common irq for McBSP ports ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmod ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data ARM: OMAP2+: HDQ1W: add custom reset function ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420 arm: omap3: clockdomain data: Remove superfluous commas from gfx_sgx_3xxx_wkdeps[] ARM: OMAP2+: powerdomain: Get rid off duplicate pwrdm_clkdm_state_switch() API ARM: OMAP3: clock data: add clockdomain for HDQ functional clock ARM: OMAP3+: dpll: Configure autoidle mode only if it's supported ARM: OMAP2+: dmtimer: cleanup iclk usage ARM: OMAP4+: Add prm and cm base init function. ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to prcm-common header ARM: OMAP3: Fix CM register bit masks ARM: OMAP: clock: convert AM3517/3505 detection/flags to AM35xx ARM: OMAP3: clock data: treat all AM35x devices the same ...
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-tauros2.c24
-rw-r--r--arch/arm/mm/proc-mohawk.S35
2 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 1fbca05..23a7643 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -108,6 +108,26 @@ static void tauros2_flush_range(unsigned long start, unsigned long end)
dsb();
}
+
+static void tauros2_disable(void)
+{
+ __asm__ __volatile__ (
+ "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
+ "mrc p15, 0, %0, c1, c0, 0\n\t"
+ "bic %0, %0, #(1 << 26)\n\t"
+ "mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t"
+ : : "r" (0x0));
+}
+
+static void tauros2_resume(void)
+{
+ __asm__ __volatile__ (
+ "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
+ "mrc p15, 0, %0, c1, c0, 0\n\t"
+ "orr %0, %0, #(1 << 26)\n\t"
+ "mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
+ : : "r" (0x0));
+}
#endif
static inline u32 __init read_extra_features(void)
@@ -194,6 +214,8 @@ void __init tauros2_init(void)
outer_cache.inv_range = tauros2_inv_range;
outer_cache.clean_range = tauros2_clean_range;
outer_cache.flush_range = tauros2_flush_range;
+ outer_cache.disable = tauros2_disable;
+ outer_cache.resume = tauros2_resume;
}
#endif
@@ -219,6 +241,8 @@ void __init tauros2_init(void)
outer_cache.inv_range = tauros2_inv_range;
outer_cache.clean_range = tauros2_clean_range;
outer_cache.flush_range = tauros2_flush_range;
+ outer_cache.disable = tauros2_disable;
+ outer_cache.resume = tauros2_resume;
}
#endif
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index b047546..fbb2124 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -345,6 +345,41 @@ ENTRY(cpu_mohawk_set_pte_ext)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
+.globl cpu_mohawk_suspend_size
+.equ cpu_mohawk_suspend_size, 4 * 6
+#ifdef CONFIG_PM_SLEEP
+ENTRY(cpu_mohawk_do_suspend)
+ stmfd sp!, {r4 - r9, lr}
+ mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
+ mrc p15, 0, r5, c15, c1, 0 @ CP access reg
+ mrc p15, 0, r6, c13, c0, 0 @ PID
+ mrc p15, 0, r7, c3, c0, 0 @ domain ID
+ mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
+ mrc p15, 0, r9, c1, c0, 0 @ control reg
+ bic r4, r4, #2 @ clear frequency change bit
+ stmia r0, {r4 - r9} @ store cp regs
+ ldmia sp!, {r4 - r9, pc}
+ENDPROC(cpu_mohawk_do_suspend)
+
+ENTRY(cpu_mohawk_do_resume)
+ ldmia r0, {r4 - r9} @ load cp regs
+ mov ip, #0
+ mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
+ mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
+ mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
+ mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+ mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
+ mcr p15, 0, r5, c15, c1, 0 @ CP access reg
+ mcr p15, 0, r6, c13, c0, 0 @ PID
+ mcr p15, 0, r7, c3, c0, 0 @ domain ID
+ orr r1, r1, #0x18 @ cache the page table in L2
+ mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
+ mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
+ mov r0, r9 @ control register
+ b cpu_resume_mmu
+ENDPROC(cpu_mohawk_do_resume)
+#endif
+
__CPUINIT
.type __mohawk_setup, #function
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