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authorCatalin Marinas <catalin.marinas@arm.com>2007-02-05 14:47:51 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 14:49:27 +0000
commite6a5d66f58431c66c79e236f722a5ad7dd959ef3 (patch)
treef2153821e15aa4f5f30d02d0bc6d9a535ea168a4 /arch/arm/mm/tlb-v6.S
parent9d99df4b10eef130dacb5f772cd589c625b03634 (diff)
downloadop-kernel-dev-e6a5d66f58431c66c79e236f722a5ad7dd959ef3.zip
op-kernel-dev-e6a5d66f58431c66c79e236f722a5ad7dd959ef3.tar.gz
[ARM] 4129/1: Add barriers after the TLB operations
The architecture specification states that TLB operations are guaranteed to be complete only after the execution of a DSB (Data Synchronisation Barrier, former Data Write Barrier or Drain Write Buffer). The branch target cache invalidation is also needed. The ISB (Instruction Synchronisation Barrier, formerly Prefetch Flush) is needed unless there will be a return from exception before the corresponding mapping is used (i.e. user mappings). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/tlb-v6.S')
-rw-r--r--arch/arm/mm/tlb-v6.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index fd6adde..20f84bb 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -53,6 +53,8 @@ ENTRY(v6wbi_flush_user_tlb_range)
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
+ mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
+ mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
mov pc, lr
/*
@@ -80,7 +82,9 @@ ENTRY(v6wbi_flush_kern_tlb_range)
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
+ mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
+ mcr p15, 0, r2, c7, c5, 4 @ prefetch flush
mov pc, lr
.section ".text.init", #alloc, #execinstr
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