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| author | Catalin Marinas <catalin.marinas@arm.com> | 2006-03-07 14:42:27 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-07 14:42:27 +0000 |
| commit | 6a0e243069b09a323255f6e847c87d531961cd96 (patch) | |
| tree | 575a7194c86b2b3e1b9db30e283a2f5705e89e99 /arch/arm/mm/tlb-v6.S | |
| parent | d11d9b2dd2c43dd99a491df8a83ae28401db0044 (diff) | |
| download | op-kernel-dev-6a0e243069b09a323255f6e847c87d531961cd96.zip op-kernel-dev-6a0e243069b09a323255f6e847c87d531961cd96.tar.gz | |
[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
Patch from Catalin Marinas
Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).
Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/tlb-v6.S')
| -rw-r--r-- | arch/arm/mm/tlb-v6.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S index 6f76b89..fd6adde 100644 --- a/arch/arm/mm/tlb-v6.S +++ b/arch/arm/mm/tlb-v6.S @@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b + mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier mov pc, lr .section ".text.init", #alloc, #execinstr |
