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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-08-26 20:28:52 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-09-20 23:33:36 +0100
commite8ce0eb5e2254b85415e4b58e73f24a5d13846a1 (patch)
tree26aaee04d5a4bb872eea215f65073825258ecd76 /arch/arm/mm/proc-xscale.S
parentf5fa68d9674156ddaafa12a058ccc93c8866d5f9 (diff)
downloadop-kernel-dev-e8ce0eb5e2254b85415e4b58e73f24a5d13846a1.zip
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ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r--arch/arm/mm/proc-xscale.S4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index fbc06e5..37dbadadf 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -548,10 +548,6 @@ ENTRY(cpu_xscale_do_resume)
mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg
mov r0, r10 @ control register
- mov r2, r8, lsr #14 @ get TTB0 base
- mov r2, r2, lsl #14
- ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
- PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
b cpu_resume_mmu
ENDPROC(cpu_xscale_do_resume)
#endif
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