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authorJens Axboe <jens.axboe@oracle.com>2010-02-22 13:48:51 +0100
committerJens Axboe <jens.axboe@oracle.com>2010-02-22 13:48:51 +0100
commitf11cbd74c5ff3614f6390b4de67a6ffdc614c378 (patch)
tree6a30920ade9eeaac5bf6d6263b5d09712e882eb0 /arch/arm/mm/proc-v7.S
parent429c42c9d246f5bda868495c09974312a0177328 (diff)
parentaea187c46f7d03ce985e55eb1398d0776a15b928 (diff)
downloadop-kernel-dev-f11cbd74c5ff3614f6390b4de67a6ffdc614c378.zip
op-kernel-dev-f11cbd74c5ff3614f6390b4de67a6ffdc614c378.tar.gz
Merge branch 'master' into for-2.6.34
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r--arch/arm/mm/proc-v7.S11
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a28521..7aaf88a 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,7 +45,14 @@ ENTRY(cpu_v7_proc_init)
ENDPROC(cpu_v7_proc_init)
ENTRY(cpu_v7_proc_fin)
- mov pc, lr
+ stmfd sp!, {lr}
+ cpsid if @ disable interrupts
+ bl v7_flush_kern_cache_all
+ mrc p15, 0, r0, c1, c0, 0 @ ctrl register
+ bic r0, r0, #0x1000 @ ...i............
+ bic r0, r0, #0x0006 @ .............ca.
+ mcr p15, 0, r0, c1, c0, 0 @ disable caches
+ ldmfd sp!, {pc}
ENDPROC(cpu_v7_proc_fin)
/*
@@ -56,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin)
* to what would be the reset vector.
*
* - loc - location to jump to for soft reset
- *
- * It is assumed that:
*/
.align 5
ENTRY(cpu_v7_reset)
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