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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-08-26 22:44:59 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-08-28 10:39:54 +0100
commit25904157168ddc8841748a729914f00e53d7e049 (patch)
tree0453e21ff7532d892e7328ebf7821fdca3a3f87b /arch/arm/mm/proc-v7.S
parentf35235a315a167e38e8e5bc9e476dcd7c932612c (diff)
downloadop-kernel-dev-25904157168ddc8841748a729914f00e53d7e049.zip
op-kernel-dev-25904157168ddc8841748a729914f00e53d7e049.tar.gz
ARM: pm: avoid writing the auxillary control register for ARMv7
For ARMv7 kernels running in the non-secure world, writing to the auxillary control register causes an abort, so we must avoid directly writing the auxillary control register. If the ACR has already been reinitialized by SoC code, don't try to restore it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r--arch/arm/mm/proc-v7.S4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a773f4e..9049c0764 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -248,7 +248,9 @@ ENTRY(cpu_v7_do_resume)
mcr p15, 0, r7, c2, c0, 0 @ TTB 0
mcr p15, 0, r8, c2, c0, 1 @ TTB 1
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
- mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
+ mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
+ teq r4, r10 @ Is it already set?
+ mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
ldr r4, =PRRR @ PRRR
ldr r5, =NMRR @ NMRR
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