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| author | Will Deacon <will.deacon@arm.com> | 2013-04-03 17:16:57 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-04-03 17:39:07 +0100 |
| commit | ae8a8b9553bd3906af74ff4e8d763904d20ab4e5 (patch) | |
| tree | 85406316a071f016d2cfcb79b4f9ef686cfa011b /arch/arm/mm/proc-v6.S | |
| parent | b00884802043d9102ecc2abfdc37a7b35b30e52a (diff) | |
| download | op-kernel-dev-ae8a8b9553bd3906af74ff4e8d763904d20ab4e5.zip op-kernel-dev-ae8a8b9553bd3906af74ff4e8d763904d20ab4e5.tar.gz | |
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead
Many ARMv7 cores have hardware page table walkers that can read the L1
cache. This is discoverable from the ID_MMFR3 register, although this
can be expensive to access from the low-level set_pte functions and is a
pain to cache, particularly with multi-cluster systems.
A useful observation is that the multi-processing extensions for ARMv7
require coherent table walks, meaning that we can make use of ALT_SMP
patching in proc-v7-* to patch away the cache flush safely for these
cores.
Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index bcaaa8d..a286d47 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -80,12 +80,10 @@ ENTRY(cpu_v6_do_idle) mov pc, lr ENTRY(cpu_v6_dcache_clean_area) -#ifndef TLB_CAN_READ_FROM_L1_CACHE 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #D_CACHE_LINE_SIZE subs r1, r1, #D_CACHE_LINE_SIZE bhi 1b -#endif mov pc, lr /* |
