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authorTrond Myklebust <Trond.Myklebust@netapp.com>2006-07-03 13:49:45 -0400
committerTrond Myklebust <Trond.Myklebust@netapp.com>2006-07-03 13:49:45 -0400
commit026477c1141b67e98e3bd8bdedb7d4b88a3ecd09 (patch)
tree2624a44924c625c367f3cebf937853b9da2de282 /arch/arm/mm/proc-sa110.S
parent9f2fa466383ce100b90fe52cb4489d7a26bf72a9 (diff)
parent29454dde27d8e340bb1987bad9aa504af7081eba (diff)
downloadop-kernel-dev-026477c1141b67e98e3bd8bdedb7d4b88a3ecd09.zip
op-kernel-dev-026477c1141b67e98e3bd8bdedb7d4b88a3ecd09.tar.gz
Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
Diffstat (limited to 'arch/arm/mm/proc-sa110.S')
-rw-r--r--arch/arm/mm/proc-sa110.S21
1 files changed, 12 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 5a760a2..c878064 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -23,6 +23,8 @@
#include <asm/pgtable.h>
#include <asm/ptrace.h>
+#include "proc-macros.S"
+
/*
* the cache line size of the I and D cache
*/
@@ -185,11 +187,12 @@ __sa110_setup:
#ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
#endif
+
+ adr r5, sa110_crval
+ ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4
- ldr r5, sa110_cr1_clear
bic r0, r0, r5
- ldr r5, sa110_cr1_set
- orr r0, r0, r5
+ orr r0, r0, r6
mov pc, lr
.size __sa110_setup, . - __sa110_setup
@@ -199,12 +202,9 @@ __sa110_setup:
* ..01 0001 ..11 1101
*
*/
- .type sa110_cr1_clear, #object
- .type sa110_cr1_set, #object
-sa110_cr1_clear:
- .word 0x3f3f
-sa110_cr1_set:
- .word 0x113d
+ .type sa110_crval, #object
+sa110_crval:
+ crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
__INITDATA
@@ -255,6 +255,9 @@ __sa110_proc_info:
PMD_SECT_CACHEABLE | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
+ .long PMD_TYPE_SECT | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
b __sa110_setup
.long cpu_arch_name
.long cpu_elf_name
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