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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-06-29 18:24:21 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-29 18:24:21 +0100 |
| commit | 8799ee9f49f6171fd58f4d64f8c067ca49006a5d (patch) | |
| tree | b746b8800bc99633f31505d151624c8ccd75cd47 /arch/arm/mm/proc-sa110.S | |
| parent | 326764a85b7676388db3ebad6488f312631d7661 (diff) | |
| download | op-kernel-dev-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.zip op-kernel-dev-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.tar.gz | |
[ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-sa110.S')
| -rw-r--r-- | arch/arm/mm/proc-sa110.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 5a760a2..31a0908 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -255,6 +255,9 @@ __sa110_proc_info: PMD_SECT_CACHEABLE | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ b __sa110_setup .long cpu_arch_name .long cpu_elf_name |
