diff options
| author | J. Bruce Fields <bfields@redhat.com> | 2010-12-17 13:29:07 -0500 |
|---|---|---|
| committer | J. Bruce Fields <bfields@redhat.com> | 2010-12-17 13:29:07 -0500 |
| commit | ec66ee3797e5848356cf593c6ec7aabf30a00cf1 (patch) | |
| tree | 7ed5c84cc914644ffa1cd1b6a2b45db53fc224e8 /arch/arm/mm/proc-macros.S | |
| parent | 1205065764f2eda3216ebe213143f69891ee3460 (diff) | |
| parent | b0c3844d8af6b9f3f18f31e1b0502fbefa2166be (diff) | |
| download | op-kernel-dev-ec66ee3797e5848356cf593c6ec7aabf30a00cf1.zip op-kernel-dev-ec66ee3797e5848356cf593c6ec7aabf30a00cf1.tar.gz | |
Merge commit 'v2.6.37-rc6' into for-2.6.38
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 7d63bea..b795afd 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -61,17 +61,27 @@ .endm /* - * cache_line_size - get the cache line size from the CSIDR register - * (available on ARMv7+). It assumes that the CSSR register was configured - * to access the L1 data cache CSIDR. + * dcache_line_size - get the minimum D-cache line size from the CTR register + * on ARMv7. */ .macro dcache_line_size, reg, tmp - mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR - and \tmp, \tmp, #7 @ cache line size encoding - mov \reg, #16 @ size offset + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word mov \reg, \reg, lsl \tmp @ actual cache line size .endm +/* + * icache_line_size - get the minimum I-cache line size from the CTR register + * on ARMv7. + */ + .macro icache_line_size, reg, tmp + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm /* * Sanity check the PTE configuration for the code below - which makes |
