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authorLennert Buytenhek <buytenh@wantstofly.org>2008-05-10 21:05:31 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-05-17 22:55:14 +0100
commitb3a8b751c1c2997653c6bf2b5d10467c39f3cc6e (patch)
tree3b41e1ba606f9f1fb1aa08d4c66b873c7443fb94 /arch/arm/mm/proc-arm940.S
parentdb2c4392907524fa376ffbd04f5781d6394e2666 (diff)
downloadop-kernel-dev-b3a8b751c1c2997653c6bf2b5d10467c39f3cc6e.zip
op-kernel-dev-b3a8b751c1c2997653c6bf2b5d10467c39f3cc6e.tar.gz
[ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode
The CPU's dma_flush_range() operation needs to clean+invalidate the given memory area if the cache is in writeback mode, or do just the invalidate part if the cache is in writethrough mode, but the current proc-arm{925,926,940,946} (incorrectly) do a cache clean in the latter case. This patch fixes that. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm940.S')
-rw-r--r--arch/arm/mm/proc-arm940.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 44ead90..1a3d63d 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -222,7 +222,7 @@ ENTRY(arm940_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
#else
- mcr p15, 0, r3, c7, c10, 2 @ clean D entry
+ mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
#endif
subs r3, r3, #1 << 26
bcs 2b @ entries 63 to 0
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