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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-11-26 12:56:21 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-12-14 14:53:22 +0000
commit2c9b9c8490b60428fa2d1c64042f7c7caed93940 (patch)
treec8af289af8c801193eea924db0cd81f09068ddb9 /arch/arm/mm/proc-arm1022.S
parentccaf5f05b218e5eb41e2f5cdfd26b18dce4a0218 (diff)
downloadop-kernel-dev-2c9b9c8490b60428fa2d1c64042f7c7caed93940.zip
op-kernel-dev-2c9b9c8490b60428fa2d1c64042f7c7caed93940.tar.gz
ARM: add size argument to __cpuc_flush_dcache_page
... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm1022.S')
-rw-r--r--arch/arm/mm/proc-arm1022.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 8eb72d7..20a5b1b 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -214,17 +214,18 @@ ENTRY(arm1022_coherent_user_range)
mov pc, lr
/*
- * flush_kern_dcache_page(void *page)
+ * flush_kern_dcache_area(void *addr, size_t size)
*
* Ensure no D cache aliasing occurs, either with itself or
* the I cache
*
- * - page - page aligned address
+ * - addr - kernel address
+ * - size - region size
*/
-ENTRY(arm1022_flush_kern_dcache_page)
+ENTRY(arm1022_flush_kern_dcache_area)
mov ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
- add r1, r0, #PAGE_SZ
+ add r1, r0, r1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
@@ -310,7 +311,7 @@ ENTRY(arm1022_cache_fns)
.long arm1022_flush_user_cache_range
.long arm1022_coherent_kern_range
.long arm1022_coherent_user_range
- .long arm1022_flush_kern_dcache_page
+ .long arm1022_flush_kern_dcache_area
.long arm1022_dma_inv_range
.long arm1022_dma_clean_range
.long arm1022_dma_flush_range
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