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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-03-26 23:35:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-04-03 16:45:49 +0100 |
| commit | 93dc68876b608da041fe40ed39424b0fcd5aa2fb (patch) | |
| tree | dcd4dc84c5a0da7ce4c1581b3ee6f81fdb969765 /arch/arm/mm/context.c | |
| parent | 6e7aceeb7c70b9ebad79bcfe91fcf738826e8e6d (diff) | |
| download | op-kernel-dev-93dc68876b608da041fe40ed39424b0fcd5aa2fb.zip op-kernel-dev-93dc68876b608da041fe40ed39424b0fcd5aa2fb.tar.gz | |
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:
1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
return code already).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/context.c')
| -rw-r--r-- | arch/arm/mm/context.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index a5a4b2bc..2ac3737 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock); static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION); static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS); -static DEFINE_PER_CPU(atomic64_t, active_asids); +DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); static cpumask_t tlb_flush_pending; @@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { local_flush_bp_all(); local_flush_tlb_all(); + dummy_flush_tlb_a15_erratum(); } atomic64_set(&per_cpu(active_asids, cpu), asid); |
