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| author | Will Deacon <will.deacon@arm.com> | 2012-04-27 13:08:53 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-05-02 11:12:49 +0100 |
| commit | c5102f5935503ebebad46e137d0eef68f272cc16 (patch) | |
| tree | 888332340ca07cbd2a648fa603b8b252af02252a /arch/arm/mm/cache-v4wt.S | |
| parent | 435a7ef52db7d86e67a009b36cac1457f8972391 (diff) | |
| download | op-kernel-dev-c5102f5935503ebebad46e137d0eef68f272cc16.zip op-kernel-dev-c5102f5935503ebebad46e137d0eef68f272cc16.tar.gz | |
ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails
The cacheflush syscall can fail for two reasons:
(1) The arguments are invalid (nonsensical address range or no VMA)
(2) The region generates a translation fault on a VIPT or PIPT cache
This patch allows do_cache_op to return an error code to userspace in
the case of the above. The various coherent_user_range implementations
are modified to return 0 in the case of VIVT caches or -EFAULT in the
case of an abort on v6/v7 cores.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v4wt.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wt.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 4d7b467..b34a5f9 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -125,6 +125,7 @@ ENTRY(v4wt_coherent_user_range) add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b + mov r0, #0 mov pc, lr /* |
