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author | Grant Likely <grant.likely@secretlab.ca> | 2012-05-08 11:35:37 -0600 |
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committer | Grant Likely <grant.likely@secretlab.ca> | 2012-05-08 11:35:37 -0600 |
commit | 7b96c686223a5c902d6a59c7d178f3904f0ab757 (patch) | |
tree | fe328ed56ad3719de3cfebad72ef74e34f1ed92b /arch/arm/mm/abort-ev6.S | |
parent | f141ed65f256ec036c7fba604da6b7c448096ef9 (diff) | |
parent | d48b97b403d23f6df0b990cee652bdf9a52337a3 (diff) | |
download | op-kernel-dev-7b96c686223a5c902d6a59c7d178f3904f0ab757.zip op-kernel-dev-7b96c686223a5c902d6a59c7d178f3904f0ab757.tar.gz |
Merge tag 'v3.4-rc6' into gpio/next
Linux 3.4-rc6
Diffstat (limited to 'arch/arm/mm/abort-ev6.S')
-rw-r--r-- | arch/arm/mm/abort-ev6.S | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index ff1f7cc..8074199 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -26,18 +26,23 @@ ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR /* - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). - * The test below covers all the write situations, including Java bytecodes + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. */ - bic r1, r1, #1 << 11 @ clear bit 11 of FSR +#ifdef CONFIG_ARM_ERRATA_326103 + ldr ip, =0x4107b36 + mrc p15, 0, r3, c0, c0, 0 @ get processor id + teq ip, r3, lsr #4 @ r0 ARM1136? + bne do_DataAbort tst r5, #PSR_J_BIT @ Java? + tsteq r5, #PSR_T_BIT @ Thumb? bne do_DataAbort - do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 - ldreq r3, [r4] @ read aborted ARM instruction + bic r1, r1, #1 << 11 @ clear bit 11 of FSR + ldr r3, [r4] @ read aborted ARM instruction #ifdef CONFIG_CPU_ENDIAN_BE8 - reveq r3, r3 + rev r3, r3 #endif do_ldrd_abort tmp=ip, insn=r3 tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. +#endif b do_DataAbort |