dmaengine: ste_dma40: Amalgamate DMA source and destination channel numbers

Devices which utilise DMA use the same device numbers for transmitting
and receiving. In this patch we encode the source and destination
information into one single attribute. We can subsequently exploit the
direction attribute to see which of the transfer directions are being
described. This also lessens the burden on platform data.

Cc: Dan Williams <djbw@fb.com>
Cc: Per Forlin <per.forlin@stericsson.com>
Cc: Rabin Vincent <rabin@rab.in>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 60 insertions, 60 deletions

diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index a30977b..7989c56 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -50,74 +50,74 @@ static struct resource dma40_resources[] = {
  */
 static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
 	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
+	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
+	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
+	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
+	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
+	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
+	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
+	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
+	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
 	/* PrimeCells - run-time configured */
-	[DB8500_DMA_DEV0_SPI0_TX] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
-	[DB8500_DMA_DEV8_SSP0_TX] = -1,
-	[DB8500_DMA_DEV9_SSP1_TX] = -1,
-	[DB8500_DMA_DEV11_UART2_TX] = -1,
-	[DB8500_DMA_DEV12_UART1_TX] = -1,
-	[DB8500_DMA_DEV13_UART0_TX] = -1,
-	[DB8500_DMA_DEV28_SD_MM2_TX] = -1,
-	[DB8500_DMA_DEV29_SD_MM0_TX] = -1,
-	[DB8500_DMA_DEV32_SD_MM1_TX] = -1,
-	[DB8500_DMA_DEV33_SPI2_TX] = -1,
-	[DB8500_DMA_DEV35_SPI1_TX] = -1,
-	[DB8500_DMA_DEV40_SPI3_TX] = -1,
-	[DB8500_DMA_DEV41_SD_MM3_TX] = -1,
-	[DB8500_DMA_DEV42_SD_MM4_TX] = -1,
-	[DB8500_DMA_DEV43_SD_MM5_TX] = -1,
-	[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
+	[DB8500_DMA_DEV0_SPI0] = -1,
+	[DB8500_DMA_DEV1_SD_MMC0] = -1,
+	[DB8500_DMA_DEV2_SD_MMC1] = -1,
+	[DB8500_DMA_DEV3_SD_MMC2] = -1,
+	[DB8500_DMA_DEV8_SSP0] = -1,
+	[DB8500_DMA_DEV9_SSP1] = -1,
+	[DB8500_DMA_DEV11_UART2] = -1,
+	[DB8500_DMA_DEV12_UART1] = -1,
+	[DB8500_DMA_DEV13_UART0] = -1,
+	[DB8500_DMA_DEV28_SD_MM2] = -1,
+	[DB8500_DMA_DEV29_SD_MM0] = -1,
+	[DB8500_DMA_DEV32_SD_MM1] = -1,
+	[DB8500_DMA_DEV33_SPI2] = -1,
+	[DB8500_DMA_DEV35_SPI1] = -1,
+	[DB8500_DMA_DEV40_SPI3] = -1,
+	[DB8500_DMA_DEV41_SD_MM3] = -1,
+	[DB8500_DMA_DEV42_SD_MM4] = -1,
+	[DB8500_DMA_DEV43_SD_MM5] = -1,
+	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
 	[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
 };
 
 /* Mapping between source event lines and physical device address */
 static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
 	/* MUSB - these will be runtime-reconfigured */
-	[DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
-	[DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
-	[DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
-	[DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
-	[DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
-	[DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
-	[DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
-	[DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
+	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
+	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
+	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
+	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
+	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
+	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
+	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
+	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
 	/* PrimeCells */
-	[DB8500_DMA_DEV0_SPI0_RX] = -1,
-	[DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
-	[DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
-	[DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
-	[DB8500_DMA_DEV8_SSP0_RX] = -1,
-	[DB8500_DMA_DEV9_SSP1_RX] = -1,
-	[DB8500_DMA_DEV11_UART2_RX] = -1,
-	[DB8500_DMA_DEV12_UART1_RX] = -1,
-	[DB8500_DMA_DEV13_UART0_RX] = -1,
-	[DB8500_DMA_DEV28_SD_MM2_RX] = -1,
-	[DB8500_DMA_DEV29_SD_MM0_RX] = -1,
-	[DB8500_DMA_DEV32_SD_MM1_RX] = -1,
-	[DB8500_DMA_DEV33_SPI2_RX] = -1,
-	[DB8500_DMA_DEV35_SPI1_RX] = -1,
-	[DB8500_DMA_DEV40_SPI3_RX] = -1,
-	[DB8500_DMA_DEV41_SD_MM3_RX] = -1,
-	[DB8500_DMA_DEV42_SD_MM4_RX] = -1,
-	[DB8500_DMA_DEV43_SD_MM5_RX] = -1,
-	[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-	[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
+	[DB8500_DMA_DEV0_SPI0] = -1,
+	[DB8500_DMA_DEV1_SD_MMC0] = -1,
+	[DB8500_DMA_DEV2_SD_MMC1] = -1,
+	[DB8500_DMA_DEV3_SD_MMC2] = -1,
+	[DB8500_DMA_DEV8_SSP0] = -1,
+	[DB8500_DMA_DEV9_SSP1] = -1,
+	[DB8500_DMA_DEV11_UART2] = -1,
+	[DB8500_DMA_DEV12_UART1] = -1,
+	[DB8500_DMA_DEV13_UART0] = -1,
+	[DB8500_DMA_DEV28_SD_MM2] = -1,
+	[DB8500_DMA_DEV29_SD_MM0] = -1,
+	[DB8500_DMA_DEV32_SD_MM1] = -1,
+	[DB8500_DMA_DEV33_SPI2] = -1,
+	[DB8500_DMA_DEV35_SPI1] = -1,
+	[DB8500_DMA_DEV40_SPI3] = -1,
+	[DB8500_DMA_DEV41_SD_MM3] = -1,
+	[DB8500_DMA_DEV42_SD_MM4] = -1,
+	[DB8500_DMA_DEV43_SD_MM5] = -1,
+	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
+	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
 };
 
 static struct stedma40_platform_data dma40_plat_data = {