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authorOlof Johansson <olof@lixom.net>2012-09-20 21:27:41 -0700
committerOlof Johansson <olof@lixom.net>2012-09-20 21:27:41 -0700
commitb612a85792192b70e6497619521772c38ace758e (patch)
tree0405e78c23b600153bee5a0e19a5129ddca832f9 /arch/arm/mach-tegra/tegra30_clocks.h
parentea832c41dacbc4a5f3888d9ef7c38213914aba2a (diff)
parent3aec092eed5d8d2b19a62b0aeed3acea9471099a (diff)
downloadop-kernel-dev-b612a85792192b70e6497619521772c38ace758e.zip
op-kernel-dev-b612a85792192b70e6497619521772c38ace758e.tar.gz
Merge branch 'next/soc' into next/multiplatform
* next/soc: (50 commits) ARM: OMAP: AM33xx hwmod: fixup SPI after platform_data move MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture ARM: bcm2835: instantiate console UART ARM: bcm2835: add stub clock driver ARM: bcm2835: add system timer ARM: bcm2835: add interrupt controller driver ARM: add infra-structure for BCM2835 and Raspberry Pi ARM: tegra20: add CPU hotplug support ARM: tegra30: add CPU hotplug support ARM: tegra: clean up the common assembly macros into sleep.h ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops ARM: tegra: introduce tegra_cpu_car_ops structures ARM: Tegra: Add smp_twd clock for Tegra20 ARM: AM33XX: clock: Add dcan clock aliases for device-tree ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions ARM: OMAP: omap_device: idle devices with no driver bound ARM: OMAP: omap_device: don't attempt late suspend if no driver bound ARM: OMAP: omap_device: keep track of driver bound status ARM: OMAP3+: hwmod: Add AM33XX HWMOD data ARM: OMAP2+: hwmod: Hook-up am33xx support in omap_hwmod framework ... Change/remove conflict in arch/arm/mach-ux500/clock.c resolved. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/tegra30_clocks.h')
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h53
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 0000000..f2f88fe
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA30_CLOCK_H
+#define __MACH_TEGRA30_CLOCK_H
+
+extern struct clk_ops tegra30_clk_32k_ops;
+extern struct clk_ops tegra30_clk_m_ops;
+extern struct clk_ops tegra_clk_m_div_ops;
+extern struct clk_ops tegra_pll_ref_ops;
+extern struct clk_ops tegra30_pll_ops;
+extern struct clk_ops tegra30_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
+extern struct clk_ops tegra30_plle_ops;
+extern struct clk_ops tegra_cml_clk_ops;
+extern struct clk_ops tegra_pciex_clk_ops;
+extern struct clk_ops tegra_sync_source_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra30_clk_double_ops;
+extern struct clk_ops tegra_clk_out_ops;
+extern struct clk_ops tegra30_super_ops;
+extern struct clk_ops tegra30_blink_clk_ops;
+extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_periph_clk_ops;
+extern struct clk_ops tegra30_dsib_clk_ops;
+extern struct clk_ops tegra_nand_clk_ops;
+extern struct clk_ops tegra_vi_clk_ops;
+extern struct clk_ops tegra_dtv_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+#endif
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