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author | Olof Johansson <olof@lixom.net> | 2011-10-12 23:52:29 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2012-02-06 18:24:58 -0800 |
commit | e2f91578b35347341482f6af9e4fcf3174531efd (patch) | |
tree | d6a739e65cfcebf70dea84527adcde2103f7ad8b /arch/arm/mach-tegra/apbio.h | |
parent | 13ae3d5bdf737d6078a562154ff4fef0ba5d0de1 (diff) | |
download | op-kernel-dev-e2f91578b35347341482f6af9e4fcf3174531efd.zip op-kernel-dev-e2f91578b35347341482f6af9e4fcf3174531efd.tar.gz |
ARM: tegra: use APB DMA for accessing APB devices
Tegra2 hangs if APB registers are accessed from the cpu during an
apb dma operation. The workaround is to use apb dma to read/write the
registers instead.
There is a dependency loop between fuses, clocks, and APBDMA. If dma
is enabled, fuse reads must go through APBDMA to avoid corruption due
to a hw bug. APBDMA requires a clock to be enabled. Clocks must read
a fuse to determine allowable cpu frequencies.
Separate out the fuse DMA initialization, and allow the fuse read
and write functions to be called without using DMA before the DMA
initialization has been completed. Access to the fuses before APBDMA
is initialized won't hit the hardware bug because nothing else can be
using DMA.
Original fuse registar access code from Varun Wadekar
<vwadekar@nvidia.com>, improved by Colin Cross <ccross@android.com>
and later moved to separate driver by Jon Mayo <jmayo@nvidia.com>.
Major refactoring/cleanup by Olof Johansson <olof@lixom.net>.
Changes since v1:
* fix 'return false' on error condition
* dequeue dma ops in case of timeout
From: Jon Mayo <jmayo@nvidia.com>.
Signed-off-by: Jon Mayo <jmayo@nvidia.com>.
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/apbio.h')
-rw-r--r-- | arch/arm/mach-tegra/apbio.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h new file mode 100644 index 0000000..8b49e8c --- /dev/null +++ b/arch/arm/mach-tegra/apbio.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2010 NVIDIA Corporation. + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_APBIO_H +#define __MACH_TEGRA_APBIO_H + +#ifdef CONFIG_TEGRA_SYSTEM_DMA + +u32 tegra_apb_readl(unsigned long offset); +void tegra_apb_writel(u32 value, unsigned long offset); + +#else +#include <asm/io.h> +#include <mach/io.h> + +static inline u32 tegra_apb_readl(unsigned long offset) +{ + return readl(IO_TO_VIRT(offset)); +} + +static inline void tegra_apb_writel(u32 value, unsigned long offset) +{ + writel(value, IO_TO_VIRT(offset)); +} +#endif + +#endif |