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authorFelipe Balbi <balbi@ti.com>2013-03-20 14:18:28 +0200
committerFelipe Balbi <balbi@ti.com>2013-03-20 19:56:21 +0200
commit75f32ec1de7a4c905ba2007972d981f96c977eb2 (patch)
tree8378105243222856b5c0fa97e1c18af9c4b447d8 /arch/arm/mach-tegra/Kconfig
parente8d891fb7b8fe4ee7311820594323d46dbc31d45 (diff)
downloadop-kernel-dev-75f32ec1de7a4c905ba2007972d981f96c977eb2.zip
op-kernel-dev-75f32ec1de7a4c905ba2007972d981f96c977eb2.tar.gz
arm: tegra: fix Kconfig select clauses
USB_ULPI and USB_ULPI_VIEWPORT shouldn't really be selected directly by anyone, but since Tegra still needs some time before turning ulpi viewport into a proper PHY driver, we need to keep the selects in place. This patch just fixes the conditional select so that it will continue to build after merging the latest PHY layer changes. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'arch/arm/mach-tegra/Kconfig')
-rw-r--r--arch/arm/mach-tegra/Kconfig8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d1c4893..dbc653e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -18,8 +18,8 @@ config ARCH_TEGRA_2x_SOC
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB
- select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select USB_ULPI if USB_PHY
+ select USB_ULPI_VIEWPORT if USB_PHY
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -37,8 +37,8 @@ config ARCH_TEGRA_3x_SOC
select PINCTRL_TEGRA30
select PL310_ERRATA_769419 if CACHE_L2X0
select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB
- select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select USB_ULPI if USB_PHY
+ select USB_ULPI_VIEWPORT if USB_PHY
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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