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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-02-21 14:57:04 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-02-21 14:57:04 -0800 |
| commit | 97b9c3e145a1ddb5a9d8115c82a8981b3f13cba2 (patch) | |
| tree | c5df11be95a5512112dd19167a75d8716a782544 /arch/arm/mach-spear3xx/include/mach/spear320.h | |
| parent | f85cca6b25971a09efbe4c6a3ae405d40c8f86da (diff) | |
| parent | 5a5af730536fbf15fc354980cba2a0400afa6b76 (diff) | |
| download | op-kernel-dev-97b9c3e145a1ddb5a9d8115c82a8981b3f13cba2.zip op-kernel-dev-97b9c3e145a1ddb5a9d8115c82a8981b3f13cba2.tar.gz | |
Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6745/1: kprobes insn decoding fix
ARM: tlb: move noMMU tlb_flush() to asm/tlb.h
ARM: tlb: delay page freeing for SMP and ARMv7 CPUs
ARM: Keep exit text/data around for SMP_ON_UP
ARM: Ensure predictable endian state on signal handler entry
ARM: 6740/1: Place correctly notes section in the linker script
ARM: 6700/1: SPEAr: Correct SOC config base address for spear320
ARM: 6722/1: SPEAr: sp810: switch to slow mode before reset
ARM: 6712/1: SPEAr: replace readl(), writel() with relaxed versions in uncompress.h
ARM: 6720/1: SPEAr: Append UL to VMALLOC_END
ARM: 6676/1: Correct the cpu_architecture() function for ARMv7
ARM: 6739/1: update .gitignore for boot/compressed
ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of broadcasted operation
ARM: 6742/1: pmu: avoid setting IRQ affinity on UP systems
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear320.h')
| -rw-r--r-- | arch/arm/mach-spear3xx/include/mach/spear320.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index cacf17a..53677e4 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -62,7 +62,7 @@ #define SPEAR320_SMII1_BASE 0xAB000000 #define SPEAR320_SMII1_SIZE 0x01000000 -#define SPEAR320_SOC_CONFIG_BASE 0xB4000000 +#define SPEAR320_SOC_CONFIG_BASE 0xB3000000 #define SPEAR320_SOC_CONFIG_SIZE 0x00000070 /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 |
