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| author | Magnus Damm <damm@opensource.se> | 2011-12-23 01:23:07 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rjw@sisk.pl> | 2011-12-25 23:39:03 +0100 |
| commit | f7dadb37931a6ffa2aa6b443188299166dc5e638 (patch) | |
| tree | e769f8b7e8a62ef1674874aa2849af6fd841b67f /arch/arm/mach-shmobile/sleep-sh7372.S | |
| parent | c656c30668b9408c46d6bfbd1eea472f39a3155d (diff) | |
| download | op-kernel-dev-f7dadb37931a6ffa2aa6b443188299166dc5e638.zip op-kernel-dev-f7dadb37931a6ffa2aa6b443188299166dc5e638.tar.gz | |
PM / shmobile: Add support for the sh7372 A4S power domain / sleep mode
The sh7372 contains a power domain named A4S which in turn
contains power domains for both I/O Devices and CPU cores.
At this point only System wide Suspend-to-RAM is supported,
but the the hardware can also support CPUIdle. With more
efforts in the future CPUIdle can work with bot A4S and A3SM.
Tested on the sh7372 Mackerel board.
[rjw: Rebased on top of the current linux-pm tree.]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch/arm/mach-shmobile/sleep-sh7372.S')
| -rw-r--r-- | arch/arm/mach-shmobile/sleep-sh7372.S | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index f3ab3c5..1d56467 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -37,13 +37,18 @@ #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) .align 12 .text - .global sh7372_resume_core_standby_a3sm -sh7372_resume_core_standby_a3sm: + .global sh7372_resume_core_standby_sysc +sh7372_resume_core_standby_sysc: ldr pc, 1f 1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET - .global sh7372_do_idle_a3sm -sh7372_do_idle_a3sm: +#define SPDCR 0xe6180008 + + /* A3SM & A4S power down */ + .global sh7372_do_idle_sysc +sh7372_do_idle_sysc: + mov r8, r0 /* sleep mode passed in r0 */ + /* * Clear the SCTLR.C bit to prevent further data cache * allocation. Clearing SCTLR.C would make all the data accesses @@ -80,13 +85,9 @@ sh7372_do_idle_a3sm: dsb dmb -#define SPDCR 0xe6180008 -#define A3SM (1 << 12) - - /* A3SM power down */ + /* SYSC power down */ ldr r0, =SPDCR - ldr r1, =A3SM - str r1, [r0] + str r8, [r0] 1: b 1b |
