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authorKukjin Kim <kgene.kim@samsung.com>2010-10-01 20:54:56 +0900
committerKukjin Kim <kgene.kim@samsung.com>2010-10-23 11:51:09 +0900
commit818ac8c134250c2f57425d1e3b3a0e19636b5506 (patch)
treeec67576a1e6feeb66f197315caed0347ba02f9d1 /arch/arm/mach-s5pv210/dev-spi.c
parente27ecd7306992fbe58ab03f20aa3452a8b40499a (diff)
downloadop-kernel-dev-818ac8c134250c2f57425d1e3b3a0e19636b5506.zip
op-kernel-dev-818ac8c134250c2f57425d1e3b3a0e19636b5506.tar.gz
ARM: S5PV210: 2nd Change to using s3c_gpio_cfgall_range()
This patch changes the code setting range of GPIO pins' configuration and pull state to use the recently introduced s3c_gpio_cfgpin_range(). NOTE: This is for missed things from the previous patch. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210/dev-spi.c')
-rw-r--r--arch/arm/mach-s5pv210/dev-spi.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
index 826cdbc..e3249a4 100644
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -35,23 +35,15 @@ static char *spi_src_clks[] = {
*/
static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP);
+ base = S5PV210_GPB(0);
break;
case 1:
- s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP);
+ base = S5PV210_GPB(4);
break;
default:
@@ -59,6 +51,9 @@ static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
return -EINVAL;
}
+ s3c_gpio_cfgall_range(base, 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
return 0;
}
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