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author | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-01 18:39:38 +0900 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-23 11:50:20 +0900 |
commit | f90715f9f07abcfff3b994a0f5b7edf7a78a5aec (patch) | |
tree | 8941ab95eadedb268124180da5b8d7f207b19aa0 /arch/arm/mach-s5p64x0/dev-spi.c | |
parent | 7008147256eebdc30329bec95ebdf99a96684f79 (diff) | |
download | op-kernel-dev-f90715f9f07abcfff3b994a0f5b7edf7a78a5aec.zip op-kernel-dev-f90715f9f07abcfff3b994a0f5b7edf7a78a5aec.tar.gz |
ARM: S5P64X0: Change to using s3c_gpio_cfgall_range()
Change the code setting a range of GPIO pins' configuration and
pull state to use the recently introduced s3c_gpio_cfgall_range().
Mop up a few missed s3c_gpio_cfgpin_range() changes.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/dev-spi.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/dev-spi.c | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c index be64fee..e78ee18 100644 --- a/arch/arm/mach-s5p64x0/dev-spi.c +++ b/arch/arm/mach-s5p64x0/dev-spi.c @@ -44,16 +44,10 @@ static int s5p6440_spi_cfg_gpio(struct platform_device *pdev) switch (pdev->id) { case 0: base = S5P6440_GPC(0); - s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP); break; case 1: base = S5P6440_GPC(4); - s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP); break; default: @@ -61,7 +55,8 @@ static int s5p6440_spi_cfg_gpio(struct platform_device *pdev) return -EINVAL; } - s3c_gpio_cfgpin_range(base, 3, S3C_GPIO_SFN(2)); + s3c_gpio_cfgall_range(base, 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); return 0; } @@ -73,16 +68,10 @@ static int s5p6450_spi_cfg_gpio(struct platform_device *pdev) switch (pdev->id) { case 0: base = S5P6450_GPC(0); - s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP); break; case 1: base = S5P6450_GPC(4); - s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP); break; default: @@ -90,7 +79,8 @@ static int s5p6450_spi_cfg_gpio(struct platform_device *pdev) return -EINVAL; } - s3c_gpio_cfgpin_range(base, 3, S3C_GPIO_SFN(2)); + s3c_gpio_cfgall_range(base, 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); return 0; } |