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authorSeungwhan Youn <sw.youn@samsung.com>2010-10-14 10:39:08 +0900
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 16:05:56 +0900
commitd4b34c6c849d67b7afaa90d55dc7fab981c72950 (patch)
treec6b5c6bfe622832865a98fecec1159cb350bc18a /arch/arm/mach-s5p64x0/clock.c
parent900fa0196c564895bfa2eb412d2a83421d3f3444 (diff)
downloadop-kernel-dev-d4b34c6c849d67b7afaa90d55dc7fab981c72950.zip
op-kernel-dev-d4b34c6c849d67b7afaa90d55dc7fab981c72950.tar.gz
ARM: S5P: Reduce duplicated EPLL control codes
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock.c')
-rw-r--r--arch/arm/mach-s5p64x0/clock.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 523ba80..b52c6e2 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,24 +73,6 @@ static const u32 clock_table[][3] = {
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
};
-int s5p64x0_epll_enable(struct clk *clk, int enable)
-{
- unsigned int ctrlbit = clk->ctrlbit;
- unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
-
- if (enable)
- __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
- else
- __raw_writel(epll_con, S5P64X0_EPLL_CON);
-
- return 0;
-}
-
-unsigned long s5p64x0_epll_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
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