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author | David S. Miller <davem@davemloft.net> | 2010-08-16 14:09:34 -0700 |
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committer | David S. Miller <davem@davemloft.net> | 2010-08-16 14:09:34 -0700 |
commit | 300a103d1504134f8c4a7e831f995e917ea9b1e4 (patch) | |
tree | 7f94d5fff513d132bd0b57a9e3bd96c4cc80d707 /arch/arm/mach-s3c64xx/setup-ide.c | |
parent | 0a492896ac07336c98f37ad7fab4a6387b6ada78 (diff) | |
parent | da5cabf80e2433131bf0ed8993abc0f7ea618c73 (diff) | |
download | op-kernel-dev-300a103d1504134f8c4a7e831f995e917ea9b1e4.zip op-kernel-dev-300a103d1504134f8c4a7e831f995e917ea9b1e4.tar.gz |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/arm/mach-s3c64xx/setup-ide.c')
-rw-r--r-- | arch/arm/mach-s3c64xx/setup-ide.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c new file mode 100644 index 0000000..c12c315 --- /dev/null +++ b/arch/arm/mach-s3c64xx/setup-ide.c @@ -0,0 +1,46 @@ +/* linux/arch/arm/mach-s3c64xx/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S3C64XX setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <plat/gpio-cfg.h> + +void s3c64xx_ide_setup_gpio(void) +{ + u32 reg; + u32 gpio = 0; + + reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); + + /* Independent CF interface, CF chip select configuration */ + writel(reg | MEM_SYS_CFG_INDEP_CF | + MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG); + + s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4)); + + /* Set XhiDATA[15:0] pins as CF Data[15:0] */ + for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5)); + + /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */ + for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6)); + + /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ + s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1)); + for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6)); +} |