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| author | Joonyoung Shim <jy0922.shim@samsung.com> | 2011-05-06 09:37:17 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-05-06 09:37:36 +0900 |
| commit | 3185847957d4834d1b30b253b1c71bb05bad7265 (patch) | |
| tree | 7a1a967a918e16ce05b581e04f1ce3b23f33d831 /arch/arm/mach-s3c64xx/dev-spi.c | |
| parent | 14587b8d4be652fccc8e0e82ae9baa4365b06d9b (diff) | |
| download | op-kernel-dev-3185847957d4834d1b30b253b1c71bb05bad7265.zip op-kernel-dev-3185847957d4834d1b30b253b1c71bb05bad7265.tar.gz | |
ARM: S3C64XX: Remove gpio-bank-X header files
The gpio-bank-X header files of S3C64XX have definitions
which can be substituted by other common GPIO API.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/dev-spi.c')
| -rw-r--r-- | arch/arm/mach-s3c64xx/dev-spi.c | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c index 405e621..82db072 100644 --- a/arch/arm/mach-s3c64xx/dev-spi.c +++ b/arch/arm/mach-s3c64xx/dev-spi.c @@ -16,7 +16,6 @@ #include <mach/dma.h> #include <mach/map.h> -#include <mach/gpio-bank-c.h> #include <mach/spi-clocks.h> #include <mach/irqs.h> @@ -40,23 +39,15 @@ static char *spi_src_clks[] = { */ static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) { + unsigned int base; + switch (pdev->id) { case 0: - s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0); - s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO); - s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO); - s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP); + base = S3C64XX_GPC(0); break; case 1: - s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1); - s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1); - s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1); - s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP); + base = S3C64XX_GPC(4); break; default: @@ -64,6 +55,9 @@ static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) return -EINVAL; } + s3c_gpio_cfgall_range(base, 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; } |
