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| author | Chris Zhong <zyw@rock-chips.com> | 2015-02-09 21:12:22 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2015-03-11 22:40:59 +0100 |
| commit | aefc7c7512455c26574ae7118429920dc3de60ae (patch) | |
| tree | 7add9a7ac1299ea35a487bd6a8428e272f98e658 /arch/arm/mach-rockchip | |
| parent | bd76d73836fa903d67eaabcb3a0201d2d0a73461 (diff) | |
| download | op-kernel-dev-aefc7c7512455c26574ae7118429920dc3de60ae.zip op-kernel-dev-aefc7c7512455c26574ae7118429920dc3de60ae.tar.gz | |
ARM: rockchip: decrease the wait time for resume
The register-default delay time for wait the 24MHz OSC stabilization as well
as PMU stabilization is 750ms, let's decrease them to a still safe 30ms.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/mach-rockchip')
| -rw-r--r-- | arch/arm/mach-rockchip/pm.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/pm.h | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index 50cb781..a3ab397 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -209,6 +209,9 @@ static int rk3288_suspend_init(struct device_node *np) memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, rk3288_bootram_sz); + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH); + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH); + return 0; } diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index 7c889c0..91a542d 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -63,6 +63,10 @@ static inline void rockchip_suspend_init(void) /* PMU_WAKEUP_CFG1 bits */ #define PMU_ARMINT_WAKEUP_EN BIT(0) +/* wait 30ms for OSC stable and 30ms for pmic stable */ +#define OSC_STABL_CNT_THRESH (32 * 30) +#define PMU_STABL_CNT_THRESH (32 * 30) + enum rk3288_pwr_mode_con { PMU_PWR_MODE_EN = 0, PMU_CLK_CORE_SRC_GATE_EN, |
