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authorHeiko Stuebner <heiko@sntech.de>2016-11-17 00:03:04 +0100
committerHeiko Stuebner <heiko@sntech.de>2017-01-06 10:29:16 +0100
commit19f0f3021e7532a1056886e3ddf524f9847e4f15 (patch)
tree575f49838b3313f585cbc909957f5a7ceba5dbdf /arch/arm/mach-rockchip
parent4c58063d4258f6beb4fd5647db6b58f49e337c8f (diff)
downloadop-kernel-dev-19f0f3021e7532a1056886e3ddf524f9847e4f15.zip
op-kernel-dev-19f0f3021e7532a1056886e3ddf524f9847e4f15.tar.gz
ARM: rockchip: drop rk3288 jtag/mmc switch handling
We moved that functionality to a more generic place where it can also be used for other socs, so drop it from architecture code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Diffstat (limited to 'arch/arm/mach-rockchip')
-rw-r--r--arch/arm/mach-rockchip/rockchip.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index a7ab9ec..ef0500a 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -29,13 +29,11 @@
#include "core.h"
#include "pm.h"
-#define RK3288_GRF_SOC_CON0 0x244
#define RK3288_TIMER6_7_PHYS 0xff810000
static void __init rockchip_timer_init(void)
{
if (of_machine_is_compatible("rockchip,rk3288")) {
- struct regmap *grf;
void __iomem *reg_base;
/*
@@ -54,16 +52,6 @@ static void __init rockchip_timer_init(void)
} else {
pr_err("rockchip: could not map timer7 registers\n");
}
-
- /*
- * Disable auto jtag/sdmmc switching that causes issues
- * with the mmc controllers making them unreliable
- */
- grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
- if (!IS_ERR(grf))
- regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
- else
- pr_err("rockchip: could not get grf syscon\n");
}
of_clk_init(NULL);
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