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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-12-02 22:07:40 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-12-02 22:07:40 +0000 |
| commit | c5b84b3bb0c055d70dc9f1b5e900378bc9d059ea (patch) | |
| tree | bd5b0b4efb552bacd812f9e6e08a29bae70c0da1 /arch/arm/mach-pxa | |
| parent | d281bc9d8a22419abc254f86a7fc268bb99914e1 (diff) | |
| parent | bc2fd1c09c226ea47ab8301cde6dbcf9e5c78b73 (diff) | |
| download | op-kernel-dev-c5b84b3bb0c055d70dc9f1b5e900378bc9d059ea.zip op-kernel-dev-c5b84b3bb0c055d70dc9f1b5e900378bc9d059ea.tar.gz | |
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
Conflicts:
arch/arm/mach-pxa/pxa25x.c
Diffstat (limited to 'arch/arm/mach-pxa')
36 files changed, 1171 insertions, 766 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 740f0a3..6755c7d 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -19,6 +19,9 @@ config CPU_PXA320 config CPU_PXA930 bool "PXA930 (codename Tavor-P)" +config CPU_PXA935 + bool "PXA935 (codename Tavor-P65)" + endmenu endif @@ -199,6 +202,10 @@ config MACH_E800 config TRIZEPS_PXA bool "PXA based Keith und Koep Trizeps DIMM-Modules" +config MACH_H5000 + bool "HP iPAQ h5000" + select PXA25x + config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" depends on TRIZEPS_PXA @@ -283,7 +290,6 @@ config MACH_MIOA701 bool "Mitac Mio A701 Support" select PXA27x select IWMMXT - select LEDS_GPIO select HAVE_PWM select GPIO_SYSFS help @@ -396,6 +402,12 @@ config PXA27x help Select code specific to PXA27x variants +config CPU_PXA26x + bool + select PXA25x + help + Select code specific to PXA26x (codename Dalhart) + config PXA3xx bool select CPU_XSC3 diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index d64c68b..dc184ea 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_MACH_MP900C) += mp900.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_MACH_COLIBRI) += colibri.o +obj-$(CONFIG_MACH_H5000) += h5000.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index a3e0e19..40b7740 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -14,7 +14,6 @@ #include <asm/clkdev.h> #include <mach/pxa2xx-regs.h> -#include <mach/pxa2xx-gpio.h> #include <mach/hardware.h> #include "devices.h" diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index deb46cd..ff0c577 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -31,7 +31,6 @@ #include <mach/mfp-pxa300.h> #include <mach/hardware.h> -#include <mach/gpio.h> #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/ohci.h> @@ -137,6 +136,10 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ GPIO85_GPIO, /* MMC WP */ GPIO99_GPIO, /* Ethernet IRQ */ + + /* Standard I2C */ + GPIO21_I2C_SCL, + GPIO22_I2C_SDA, }; #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 65558d6..c5e28a4 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -19,6 +19,7 @@ #include <linux/fs.h> #include <linux/interrupt.h> #include <linux/mmc/host.h> +#include <linux/mtd/physmap.h> #include <linux/pm.h> #include <linux/gpio.h> #include <linux/backlight.h> @@ -541,11 +542,42 @@ err_free_1: static inline void corgi_init_spi(void) {} #endif +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00120000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &corgiscoop_device, &corgifb_device, &corgikbd_device, &corgiled_device, + &sharpsl_rom_device, }; static void corgi_poweroff(void) diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 1f272ea..771dd4e 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c @@ -64,7 +64,7 @@ typedef struct { /* Define the refresh period in mSec for the SDRAM and the number of rows */ #define SDRAM_TREF 64 /* standard 64ms SDRAM */ -#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ +static unsigned int sdram_rows; #define CCLKCFG_TURBO 0x1 #define CCLKCFG_FCS 0x2 @@ -73,6 +73,9 @@ typedef struct { #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) #define MDREFR_DRI_MASK 0xFFF +#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) +#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) + /* * PXA255 definitions */ @@ -109,6 +112,10 @@ static struct cpufreq_frequency_table static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; +static unsigned int pxa255_turbo_table; +module_param(pxa255_turbo_table, uint, 0); +MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); + /* * PXA270 definitions * @@ -158,22 +165,16 @@ static struct cpufreq_frequency_table extern unsigned get_clk_frequency_khz(int info); -static void find_freq_tables(struct cpufreq_policy *policy, - struct cpufreq_frequency_table **freq_table, +static void find_freq_tables(struct cpufreq_frequency_table **freq_table, pxa_freqs_t **pxa_freqs) { if (cpu_is_pxa25x()) { - if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { + if (!pxa255_turbo_table) { *pxa_freqs = pxa255_run_freqs; *freq_table = pxa255_run_freq_table; - } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { + } else { *pxa_freqs = pxa255_turbo_freqs; *freq_table = pxa255_turbo_freq_table; - } else { - printk("CPU PXA: Unknown policy found. " - "Using CPUFREQ_POLICY_PERFORMANCE\n"); - *pxa_freqs = pxa255_run_freqs; - *freq_table = pxa255_run_freq_table; } } if (cpu_is_pxa27x()) { @@ -194,14 +195,28 @@ static void pxa27x_guess_max_freq(void) } } +static void init_sdram_rows(void) +{ + uint32_t mdcnfg = MDCNFG; + unsigned int drac2 = 0, drac0 = 0; + + if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) + drac2 = MDCNFG_DRAC2(mdcnfg); + + if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) + drac0 = MDCNFG_DRAC0(mdcnfg); + + sdram_rows = 1 << (11 + max(drac0, drac2)); +} + static u32 mdrefr_dri(unsigned int freq) { u32 dri = 0; if (cpu_is_pxa25x()) - dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32)); + dri = ((freq * SDRAM_TREF) / (sdram_rows * 32)); if (cpu_is_pxa27x()) - dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32; + dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32; return dri; } @@ -212,7 +227,7 @@ static int pxa_verify_policy(struct cpufreq_policy *policy) pxa_freqs_t *pxa_freqs; int ret; - find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs); + find_freq_tables(&pxa_freqs_table, &pxa_freqs); ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); if (freq_debug) @@ -240,7 +255,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; /* Get the current policy */ - find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings); + find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); /* Lookup the next frequency */ if (cpufreq_frequency_table_target(policy, pxa_freqs_table, @@ -329,11 +344,15 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) { int i; unsigned int freq; + struct cpufreq_frequency_table *pxa255_freq_table; + pxa_freqs_t *pxa255_freqs; /* try to guess pxa27x cpu */ if (cpu_is_pxa27x()) pxa27x_guess_max_freq(); + init_sdram_rows(); + /* set default policy and cpuinfo */ policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ policy->cur = get_clk_frequency_khz(0); /* current freq */ @@ -354,6 +373,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) } pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; + pxa255_turbo_table = !!pxa255_turbo_table; + /* Generate the pxa27x cpufreq_frequency_table struct */ for (i = 0; i < NUM_PXA27x_FREQS; i++) { freq = pxa27x_freqs[i].khz; @@ -368,8 +389,12 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) * Set the policy's minimum and maximum frequencies from the tables * just constructed. This sets cpuinfo.mxx_freq, min and max. */ - if (cpu_is_pxa25x()) - cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table); + if (cpu_is_pxa25x()) { + find_freq_tables(&pxa255_freq_table, &pxa255_freqs); + pr_info("PXA255 cpufreq using %s frequency table\n", + pxa255_turbo_table ? "turbo" : "run"); + cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table); + } else if (cpu_is_pxa27x()) cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 35736fc..e16f8e3 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -4,13 +4,12 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <mach/gpio.h> +#include <mach/pxa-regs.h> #include <mach/udc.h> #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/irda.h> #include <mach/i2c.h> -#include <mach/mfp-pxa27x.h> #include <mach/ohci.h> #include <mach/pxa27x_keypad.h> #include <mach/pxa2xx_spi.h> @@ -156,8 +155,8 @@ void __init set_pxa_fb_parent(struct device *parent_dev) static struct resource pxa_resource_ffuart[] = { { - .start = __PREG(FFUART), - .end = __PREG(FFUART) + 35, + .start = 0x40100000, + .end = 0x40100023, .flags = IORESOURCE_MEM, }, { .start = IRQ_FFUART, @@ -175,8 +174,8 @@ struct platform_device pxa_device_ffuart= { static struct resource pxa_resource_btuart[] = { { - .start = __PREG(BTUART), - .end = __PREG(BTUART) + 35, + .start = 0x40200000, + .end = 0x40200023, .flags = IORESOURCE_MEM, }, { .start = IRQ_BTUART, @@ -194,8 +193,8 @@ struct platform_device pxa_device_btuart = { static struct resource pxa_resource_stuart[] = { { - .start = __PREG(STUART), - .end = __PREG(STUART) + 35, + .start = 0x40700000, + .end = 0x40700023, .flags = IORESOURCE_MEM, }, { .start = IRQ_STUART, @@ -213,8 +212,8 @@ struct platform_device pxa_device_stuart = { static struct resource pxa_resource_hwuart[] = { { - .start = __PREG(HWUART), - .end = __PREG(HWUART) + 47, + .start = 0x41600000, + .end = 0x4160002F, .flags = IORESOURCE_MEM, }, { .start = IRQ_HWUART, @@ -249,18 +248,53 @@ struct platform_device pxa_device_i2c = { .num_resources = ARRAY_SIZE(pxai2c_resources), }; -static unsigned long pxa27x_i2c_mfp_cfg[] = { - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, -}; - void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) { - if (cpu_is_pxa27x()) - pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg)); pxa_register_device(&pxa_device_i2c, info); } +#ifdef CONFIG_PXA27x +static struct resource pxa27x_resources_i2c_power[] = { + { + .start = 0x40f00180, + .end = 0x40f001a3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PWRI2C, + .end = IRQ_PWRI2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa27x_device_i2c_power = { + .name = "pxa2xx-i2c", + .id = 1, + .resource = pxa27x_resources_i2c_power, + .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power), +}; +#endif + +#ifdef CONFIG_PXA3xx +static struct resource pxa3xx_resources_i2c_power[] = { + { + .start = 0x40f500c0, + .end = 0x40f500d3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PWRI2C, + .end = IRQ_PWRI2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa3xx_device_i2c_power = { + .name = "pxa2xx-i2c", + .id = 1, + .resource = pxa3xx_resources_i2c_power, + .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), +}; +#endif + static struct resource pxai2s_resources[] = { { .start = 0x40400000, @@ -296,11 +330,36 @@ void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) pxa_register_device(&pxa_device_ficp, info); } -struct platform_device pxa_device_rtc = { +static struct resource pxa_rtc_resources[] = { + [0] = { + .start = 0x40900000, + .end = 0x40900000 + 0x3b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC1Hz, + .end = IRQ_RTC1Hz, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTCAlrm, + .end = IRQ_RTCAlrm, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device sa1100_device_rtc = { .name = "sa1100-rtc", .id = -1, }; +struct platform_device pxa_device_rtc = { + .name = "pxa-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(pxa_rtc_resources), + .resource = pxa_rtc_resources, +}; + static struct resource pxa_ac97_resources[] = { [0] = { .start = 0x40500000, diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index bb04af4..ecc24a4 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -11,6 +11,7 @@ extern struct platform_device pxa_device_hwuart; extern struct platform_device pxa_device_i2c; extern struct platform_device pxa_device_i2s; extern struct platform_device pxa_device_ficp; +extern struct platform_device sa1100_device_rtc; extern struct platform_device pxa_device_rtc; extern struct platform_device pxa_device_ac97; diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 83c56d3..3e6aa33 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -113,6 +113,10 @@ static unsigned long ezx_pin_config[] __initdata = { GPIO91_USB_P3_1, /* ICL_XRXD */ GPIO56_USB_P3_4, /* ICL_VMOUT */ GPIO113_USB_P3_3, /* /ICL_VMIN */ + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, }; static void __init ezx_init(void) diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 14930cf..5fec1e4 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c @@ -25,6 +25,18 @@ #include "generic.h" +#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) +#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) +#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) +#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) + +#define GPLR_OFFSET 0x00 +#define GPDR_OFFSET 0x0C +#define GPSR_OFFSET 0x18 +#define GPCR_OFFSET 0x24 +#define GRER_OFFSET 0x30 +#define GFER_OFFSET 0x3C +#define GEDR_OFFSET 0x48 struct pxa_gpio_chip { struct gpio_chip chip; @@ -33,6 +45,18 @@ struct pxa_gpio_chip { int pxa_last_gpio; +#ifdef CONFIG_CPU_PXA26x +/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, + * as well as their Alternate Function value being '1' for GPIO in GAFRx. + */ +static int __gpio_is_inverted(unsigned gpio) +{ + return cpu_is_pxa25x() && gpio > 85; +} +#else +#define __gpio_is_inverted(gpio) (0) +#endif + /* * Configure pins for GPIO or other functions */ @@ -75,7 +99,10 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) gpdr = pxa->regbase + GPDR_OFFSET; local_irq_save(flags); value = __raw_readl(gpdr); - value &= ~mask; + if (__gpio_is_inverted(chip->base + offset)) + value |= mask; + else + value &= ~mask; __raw_writel(value, gpdr); local_irq_restore(flags); @@ -97,7 +124,10 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip, gpdr = pxa->regbase + GPDR_OFFSET; local_irq_save(flags); tmp = __raw_readl(gpdr); - tmp |= mask; + if (__gpio_is_inverted(chip->base + offset)) + tmp &= ~mask; + else + tmp |= mask; __raw_writel(tmp, gpdr); local_irq_restore(flags); @@ -173,10 +203,17 @@ static unsigned long GPIO_IRQ_mask[4]; */ static int __gpio_is_occupied(unsigned gpio) { - if (cpu_is_pxa25x() || cpu_is_pxa27x()) - return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2)); - else - return 0; + if (cpu_is_pxa27x() || cpu_is_pxa25x()) { + int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; + int dir = GPDR(gpio) & GPIO_bit(gpio); + + if (__gpio_is_inverted(gpio)) + return af != 1 || dir == 0; + else + return af != 0 || dir != 0; + } + + return 0; } static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) @@ -190,9 +227,8 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) /* Don't mess with enabled GPIOs using preconfigured edges or * GPIOs set to alternate function or to output during probe */ - if ((GPIO_IRQ_rising_edge[idx] | - GPIO_IRQ_falling_edge[idx] | - GPDR(gpio)) & GPIO_bit(gpio)) + if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || + (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) return 0; if (__gpio_is_occupied(gpio)) @@ -201,7 +237,10 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; } - GPDR(gpio) &= ~GPIO_bit(gpio); + if (__gpio_is_inverted(gpio)) + GPDR(gpio) |= GPIO_bit(gpio); + else + GPDR(gpio) &= ~GPIO_bit(gpio); if (type & IRQ_TYPE_EDGE_RISING) __set_bit(gpio, GPIO_IRQ_rising_edge); diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c new file mode 100644 index 0000000..da6e442 --- /dev/null +++ b/arch/arm/mach-pxa/h5000.c @@ -0,0 +1,200 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright 2000-2003 Hewlett-Packard Company. + * Copyright 2002 Jamey Hicks <jamey.hicks@hp.com> + * Copyright 2004-2005 Phil Blundell <pb@handhelds.org> + * Copyright 2007-2008 Anton Vorontsov <cbouatmailru@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/h5000.h> +#include <mach/pxa-regs.h> +#include <mach/pxa2xx-regs.h> +#include <mach/mfp-pxa25x.h> +#include <mach/udc.h> +#include "generic.h" + +/* + * Flash + */ + +static struct mtd_partition h5000_flash0_partitions[] = { + { + .name = "bootldr", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "root", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +static struct mtd_partition h5000_flash1_partitions[] = { + { + .name = "second root", + .size = SZ_16M - 0x00040000, + .offset = 0, + }, + { + .name = "asset", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct physmap_flash_data h5000_flash0_data = { + .width = 4, + .parts = h5000_flash0_partitions, + .nr_parts = ARRAY_SIZE(h5000_flash0_partitions), +}; + +static struct physmap_flash_data h5000_flash1_data = { + .width = 4, + .parts = h5000_flash1_partitions, + .nr_parts = ARRAY_SIZE(h5000_flash1_partitions), +}; + +static struct resource h5000_flash0_resources = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, +}; + +static struct resource h5000_flash1_resources = { + .start = PXA_CS0_PHYS + SZ_32M, + .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, +}; + +static struct platform_device h5000_flash[] = { + { + .name = "physmap-flash", + .id = 0, + .resource = &h5000_flash0_resources, + .num_resources = 1, + .dev = { + .platform_data = &h5000_flash0_data, + }, + }, + { + .name = "physmap-flash", + .id = 1, + .resource = &h5000_flash1_resources, + .num_resources = 1, + .dev = { + .platform_data = &h5000_flash1_data, + }, + }, +}; + +/* + * USB Device Controller + */ + +static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = { + .gpio_pullup = H5000_GPIO_USB_PULLUP, +}; + +/* + * GPIO setup + */ + +static unsigned long h5000_pin_config[] __initdata = { + /* Crystal and Clock Signals */ + GPIO12_32KHz, + + /* SDRAM and Static Memory I/O Signals */ + GPIO15_nCS_1, + GPIO78_nCS_2, + GPIO79_nCS_3, + GPIO80_nCS_4, + + /* FFUART */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO36_FFUART_DCD, + GPIO37_FFUART_DSR, + GPIO38_FFUART_RI, + GPIO39_FFUART_TXD, + GPIO40_FFUART_DTR, + GPIO41_FFUART_RTS, + + /* BTUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + GPIO45_BTUART_RTS, + + /* SSP1 */ + GPIO23_SSP1_SCLK, + GPIO25_SSP1_TXD, + GPIO26_SSP1_RXD, +}; + +/* + * Localbus setup: + * CS0: Flash; + * CS1: MediaQ chip, select 16-bit bus and vlio; + * CS5: SAMCOP. + */ + +static void fix_msc(void) +{ + MSC0 = 0x129c24f2; + MSC1 = 0x7ff424fa; + MSC2 = 0x7ff47ff4; + + MDREFR |= 0x02080000; +} + +/* + * Platform devices + */ + +static struct platform_device *devices[] __initdata = { + &h5000_flash[0], + &h5000_flash[1], +}; + +static void __init h5000_init(void) +{ + fix_msc(); + + pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config)); + pxa_set_udc_info(&h5000_udc_mach_info); + platform_add_devices(ARRAY_AND_SIZE(devices)); +} + +MACHINE_START(H5400, "HP iPAQ H5000") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .timer = &pxa_timer, + .init_machine = h5000_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h new file mode 100644 index 0000000..2a5ae38 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/h5000.h @@ -0,0 +1,113 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright(20)02 Hewlett-Packard Company. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks + */ + +#ifndef __ASM_ARCH_H5000_H +#define __ASM_ARCH_H5000_H + +#include <mach/mfp-pxa25x.h> + +/* + * CPU GPIOs + */ + +#define H5000_GPIO_POWER_BUTTON (0) +#define H5000_GPIO_RESET_BUTTON_N (1) +#define H5000_GPIO_OPT_INT (2) +#define H5000_GPIO_BACKUP_POWER (3) +#define H5000_GPIO_ACTION_BUTTON (4) +#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ +/* 6 not connected */ +#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ +/* 8 not connected */ +#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ +#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ +#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ +/*(12) not connected */ +#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ +#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ +/*(15) is CS1# */ +/*(16) not connected */ +/*(17) not connected */ +/*(18) is pcmcia ready */ +/*(19) is dreq1 */ +/*(20) is dreq0 */ +#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ +/*(22) is not connected */ +#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ +/*(27) not connected */ +#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ +/*(33) is CS5# */ +#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ + +#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ + +#define H5000_GPIO_IRDA_RXD (46) +#define H5000_GPIO_IRDA_TXD (47) + +#define H5000_GPIO_POE_N (48) /* used for pcmcia */ +#define H5000_GPIO_PWE_N (49) /* used for pcmcia */ +#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ +#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ +#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ +#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ +#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ +#define H5000_GPIO_PREG_N (55) /* used for pcmcia */ +#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ +#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ + +#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ +/*(59) not connected */ +#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ +#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ +#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ +/*(63) is not connected */ +#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ +#define H5000_GPIO_CHG_EN (65) /* to sc801 en */ +#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ +#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ +#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ +/*(69) is not connected */ +#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ +#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) +#define H5000_GPIO_BT_M_RESET (72) +#define H5000_GPIO_STD_CHG_RATE (73) +#define H5000_GPIO_SD_WP_N (74) +#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ +#define H5000_GPIO_HEADPHONE_DETECT (76) +#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ +/*(78) is CS2# */ +/*(79) is CS3# */ +/*(80) is CS4# */ + +#endif /* __ASM_ARCH_H5000_H */ diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index a582a6d..e2d6784 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -102,6 +102,9 @@ * PXA930 B0 0x69056835 0x5E643013 * PXA930 B1 0x69056837 0x7E643013 * PXA930 B2 0x69056838 0x8E643013 + * + * PXA935 A0 0x56056931 0x1E653013 + * PXA935 B0 0x56056936 0x6E653013 */ #ifdef CONFIG_PXA25x #define __cpu_is_pxa210(id) \ @@ -178,12 +181,22 @@ #define __cpu_is_pxa930(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x683; \ + _id == 0x683; \ }) #else #define __cpu_is_pxa930(id) (0) #endif +#ifdef CONFIG_CPU_PXA935 +#define __cpu_is_pxa935(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x693; \ + }) +#else +#define __cpu_is_pxa935(id) (0) +#endif + #define cpu_is_pxa210() \ ({ \ __cpu_is_pxa210(read_cpuid_id()); \ @@ -204,8 +217,6 @@ __cpu_is_pxa25x(read_cpuid_id()); \ }) -extern int cpu_is_pxa26x(void); - #define cpu_is_pxa27x() \ ({ \ __cpu_is_pxa27x(read_cpuid_id()); \ @@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void); __cpu_is_pxa930(id); \ }) +#define cpu_is_pxa935() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa935(id); \ + }) + /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x @@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void); _id == 0x3; \ }) +#define __cpu_is_pxa9xx(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x683 || _id == 0x693; \ + }) + #define cpu_is_pxa2xx() \ ({ \ __cpu_is_pxa2xx(read_cpuid_id()); \ @@ -259,21 +282,10 @@ extern int cpu_is_pxa26x(void); __cpu_is_pxa3xx(read_cpuid_id()); \ }) -/* - * Handy routine to set GPIO alternate functions - */ -extern int pxa_gpio_mode( int gpio_mode ); - -/* - * Return GPIO level, nonzero means high, zero is low - */ -extern int pxa_gpio_get_value(unsigned gpio); - -/* - * Set output GPIO level - */ -extern void pxa_gpio_set_value(unsigned gpio, int value); - +#define cpu_is_pxa9xx() \ + ({ \ + __cpu_is_pxa9xx(read_cpuid_id()); \ + }) /* * return current memory and LCD clock frequency in units of 10kHz */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index 617cab2..a72869b 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h @@ -158,4 +158,35 @@ #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) +#ifdef CONFIG_CPU_PXA26x +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) + +/* SDRAM */ +#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) +#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) +#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) +#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) + +/* USB */ +#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) +#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) +#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) +#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) +#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) + +/* ASSP */ +#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) +#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) +#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) +#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) +#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) +#endif + #endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index 122bdbd..da4f85a 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -11,6 +11,12 @@ #include <mach/mfp.h> #include <mach/mfp-pxa2xx.h> +/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN + * bit is set, regardless of the GPIO configuration + */ +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) + /* GPIO */ #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h index 8483cb5..0286844 100644 --- a/arch/arm/mach-pxa/include/mach/mioa701.h +++ b/arch/arm/mach-pxa/include/mach/mioa701.h @@ -10,12 +10,14 @@ (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) /* Global GPIOs */ -#define GPIO9_CHARGE_nEN 9 +#define GPIO9_CHARGE_EN 9 #define GPIO18_POWEROFF 18 #define GPIO87_LCD_POWER 87 +#define GPIO96_AC_DETECT 96 +#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ /* USB */ -#define GPIO13_USB_DETECT 13 +#define GPIO13_nUSB_DETECT 13 #define GPIO22_USB_ENABLE 22 /* SDIO bits */ @@ -24,7 +26,10 @@ #define GPIO91_SDIO_EN 91 /* Bluetooth */ +#define GPIO14_BT_nACTIVITY 14 #define GPIO83_BT_ON 83 +#define GPIO77_BT_UNKNOWN1 77 +#define GPIO86_BT_MAYBE_nRESET 86 /* GPS */ #define GPIO23_GPS_UNKNOWN1 23 diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index 15295d9..31d615a 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -13,6 +13,7 @@ #ifndef __PXA_REGS_H #define __PXA_REGS_H +#include <mach/hardware.h> /* * PXA Chip selects @@ -123,298 +124,6 @@ #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -/* - * UARTs - */ - -/* Full Function UART (FFUART) */ -#define FFUART FFRBR -#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ -#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ -#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ -#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ -#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ -#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ -#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ -#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ -#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ -#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ -#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ -#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Bluetooth UART (BTUART) */ -#define BTUART BTRBR -#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ -#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ -#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ -#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ -#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ -#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ -#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ -#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ -#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ -#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ -#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ -#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Standard UART (STUART) */ -#define STUART STRBR -#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ -#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ -#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ -#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ -#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ -#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ -#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ -#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ -#define STMSR __REG(0x40700018) /* Reserved */ -#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ -#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ -#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Hardware UART (HWUART) */ -#define HWUART HWRBR -#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ -#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ -#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ -#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ -#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ -#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ -#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ -#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ -#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ -#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ -#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ -#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ -#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ -#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ -#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -/* - * IrSR (Infrared Selection Register) - */ -#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ -#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ -#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ -#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ -#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ - - -/* - * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c - */ - -/* - * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c - */ - -/* - * AC97 Controller registers - */ - -#define POCR __REG(0x40500000) /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define PICR __REG(0x40500004) /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MCCR __REG(0x40500008) /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define GCR __REG(0x4050000C) /* Global Control Register */ -#ifdef CONFIG_PXA3xx -#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ -#endif -#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR __REG(0x40500010) /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ -#define POSR_FSR (1 << 2) /* FIFO Service Request */ - -#define PISR __REG(0x40500014) /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ -#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define PISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MCSR __REG(0x40500018) /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ -#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MCSR_FSR (1 << 2) /* FIFO Service Request */ - -#define GSR __REG(0x4050001C) /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR __REG(0x40500020) /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ -#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ - -#define MOCR __REG(0x40500100) /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ -#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MICR __REG(0x40500108) /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ -#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MOSR __REG(0x40500110) /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ -#define MOSR_FSR (1 << 2) /* FIFO Service Request */ - -#define MISR __REG(0x40500118) /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ -#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ - -#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ -#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ -#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ -#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ - - -/* - * Fast Infrared Communication Port - */ - -#define FICP __REG(0x40800000) /* Start of FICP area */ -#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ -#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ -#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ -#define ICDR __REG(0x4080000c) /* ICP Data Register */ -#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ -#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ - -#define ICCR0_AME (1 << 7) /* Address match enable */ -#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ -#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ -#define ICCR0_RXE (1 << 4) /* Receive enable */ -#define ICCR0_TXE (1 << 3) /* Transmit enable */ -#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ -#define ICCR0_LBM (1 << 1) /* Loopback mode */ -#define ICCR0_ITR (1 << 0) /* IrDA transmission */ - -#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ -#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ -#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ -#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ -#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ -#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ - -#ifdef CONFIG_PXA27x -#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ -#endif -#define ICSR0_FRE (1 << 5) /* Framing error */ -#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ -#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ -#define ICSR0_RAB (1 << 2) /* Receiver abort */ -#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ -#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ - -#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ -#define ICSR1_CRE (1 << 5) /* CRC error */ -#define ICSR1_EOF (1 << 4) /* End of frame */ -#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ -#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ -#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ -#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ - - /* * Real Time Clock */ @@ -463,19 +172,6 @@ /* - * Pulse Width Modulator - */ - -#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ -#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ - -#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ -#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ - - -/* * Interrupt Controller */ @@ -496,19 +192,6 @@ * General Purpose I/O */ -#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) -#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) -#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) -#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ @@ -558,10 +241,6 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) - -/* Interrupt Controller */ - #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) @@ -580,189 +259,5 @@ #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#endif - -/* - * Power Manager - see pxa2xx-regs.h - */ - -/* - * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h - */ - -/* - * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h - */ - -/* - * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h - */ - -#ifdef CONFIG_PXA27x - -/* Camera Interface */ -#define CICR0 __REG(0x50000000) -#define CICR1 __REG(0x50000004) -#define CICR2 __REG(0x50000008) -#define CICR3 __REG(0x5000000C) -#define CICR4 __REG(0x50000010) -#define CISR __REG(0x50000014) -#define CIFR __REG(0x50000018) -#define CITOR __REG(0x5000001C) -#define CIBR0 __REG(0x50000028) -#define CIBR1 __REG(0x50000030) -#define CIBR2 __REG(0x50000038) - -#define CICR0_DMAEN (1 << 31) /* DMA request enable */ -#define CICR0_PAR_EN (1 << 30) /* Parity enable */ -#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ -#define CICR0_ENB (1 << 28) /* Camera interface enable */ -#define CICR0_DIS (1 << 27) /* Camera interface disable */ -#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ -#define CICR0_TOM (1 << 9) /* Time-out mask */ -#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ -#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ -#define CICR0_EOLM (1 << 6) /* End-of-line mask */ -#define CICR0_PERRM (1 << 5) /* Parity-error mask */ -#define CICR0_QDM (1 << 4) /* Quick-disable mask */ -#define CICR0_CDM (1 << 3) /* Disable-done mask */ -#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ -#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ -#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ - -#define CICR1_TBIT (1 << 31) /* Transparency bit */ -#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ -#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ -#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ -#define CICR1_RGB_F (1 << 11) /* RGB format */ -#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ -#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ -#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ -#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ -#define CICR1_DW (0x7 << 0) /* Data width mask */ - -#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock - wait count mask */ -#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock - wait count mask */ -#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ -#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock - wait count mask */ -#define CICR2_FSW (0x7 << 0) /* Frame stabilization - wait count mask */ - -#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock - wait count mask */ -#define CICR3_EFW (0xff << 16) /* End-of-frame line clock - wait count mask */ -#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ -#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock - wait count mask */ -#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ - -#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ -#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ -#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ -#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ -#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ -#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ -#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ -#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ - -#define CISR_FTO (1 << 15) /* FIFO time-out */ -#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ -#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ -#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ -#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ -#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ -#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ -#define CISR_EOL (1 << 8) /* End of line */ -#define CISR_PAR_ERR (1 << 7) /* Parity error */ -#define CISR_CQD (1 << 6) /* Camera interface quick disable */ -#define CISR_CDD (1 << 5) /* Camera interface disable done */ -#define CISR_SOF (1 << 4) /* Start of frame */ -#define CISR_EOF (1 << 3) /* End of frame */ -#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ -#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ -#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ - -#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ -#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ -#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ -#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ -#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ -#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ -#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ -#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ - -#define SRAM_SIZE 0x40000 /* 4x64K */ - -#define SRAM_MEM_PHYS 0x5C000000 - -#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ -#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ - -#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ -#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ -#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ -#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ - -#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ -#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ -#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ -#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ - -#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ -#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ -#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ -#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ - -#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ -#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ -#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ -#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ - -#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ -#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ -#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ -#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ - -#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ - -#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ -#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ -#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ - -#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ -#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ -#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ - -#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ -#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ -#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ - -#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ -#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ -#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ - -#endif - -/* PWRMODE register M field values */ - -#define PWRMODE_IDLE 0x1 -#define PWRMODE_STANDBY 0x2 -#define PWRMODE_SLEEP 0x3 -#define PWRMODE_DEEPSLEEP 0x7 #endif diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h index 6ef1dd0..d83393e 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h @@ -365,4 +365,9 @@ #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) +/* + * Handy routine to set GPIO alternate functions + */ +extern int pxa_gpio_mode( int gpio_mode ); + #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 806ecfe..77102d6 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -49,6 +49,11 @@ #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ @@ -243,4 +248,11 @@ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ +/* PWRMODE register M field values */ + +#define PWRMODE_IDLE 0x1 +#define PWRMODE_STANDBY 0x2 +#define PWRMODE_SLEEP 0x3 +#define PWRMODE_DEEPSLEEP 0x7 + #endif diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 0000000..e41b9d2 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h @@ -0,0 +1,99 @@ +#ifndef __ASM_ARCH_REGS_AC97_H +#define __ASM_ARCH_REGS_AC97_H + +/* + * AC97 Controller registers + */ + +#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define GCR __REG(0x4050000C) /* Global Control Register */ +#ifdef CONFIG_PXA3xx +#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ +#endif +#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ + +#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR_FIFOE (1 << 4) /* FIFO error */ +#define POSR_FSR (1 << 2) /* FIFO Service Request */ + +#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR_FIFOE (1 << 4) /* FIFO error */ +#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define PISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR_FIFOE (1 << 4) /* FIFO error */ +#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MCSR_FSR (1 << 2) /* FIFO Service Request */ + +#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR_CDONE (1 << 19) /* Command Done */ +#define GSR_SDONE (1 << 18) /* Status Done */ +#define GSR_RDCS (1 << 15) /* Read Completion Status */ +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ +#define GSR_PCR (1 << 8) /* Primary Codec Ready */ +#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ +#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ + +#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ + +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ + +#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR_FEIE (1 << 3) /* FIFO Error */ +#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR_FEIE (1 << 3) /* FIFO Error */ +#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR_FIFOE (1 << 4) /* FIFO error */ +#define MOSR_FSR (1 << 2) /* FIFO Service Request */ + +#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR_FIFOE (1 << 4) /* FIFO error */ +#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ + +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + +#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h new file mode 100644 index 0000000..55aeb7f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-uart.h @@ -0,0 +1,143 @@ +#ifndef __ASM_ARCH_REGS_UART_H +#define __ASM_ARCH_REGS_UART_H + +/* + * UARTs + */ + +/* Full Function UART (FFUART) */ +#define FFUART FFRBR +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Bluetooth UART (BTUART) */ +#define BTUART BTRBR +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Standard UART (STUART) */ +#define STUART STRBR +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ +#define STMSR __REG(0x40700018) /* Reserved */ +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Hardware UART (HWUART) */ +#define HWUART HWRBR +#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ +#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ +#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ +#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ +#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ +#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ +#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ +#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ +#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ +#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ +#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ +#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ +#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ +#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ +#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + +/* + * IrSR (Infrared Selection Register) + */ +#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ +#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ +#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ +#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ +#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ + +#endif /* __ASM_ARCH_REGS_UART_H */ diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 21e3e89..a9a4f30 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -10,7 +10,7 @@ */ #include <linux/serial_reg.h> -#include <mach/pxa-regs.h> +#include <mach/regs-uart.h> #include <asm/mach-types.h> #define __REG(x) ((volatile unsigned long *)x) diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index b4d00ab..5609f52 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -20,6 +20,7 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/clk.h> +#include <linux/gpio.h> #include <linux/spi/spi.h> #include <linux/smc91x.h> @@ -36,7 +37,6 @@ #include <mach/pxa-regs.h> #include <mach/mfp-pxa300.h> -#include <mach/gpio.h> #include <mach/pxafb.h> #include <mach/ssp.h> #include <mach/pxa2xx_spi.h> diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 519138b..bf59cec 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -123,6 +123,10 @@ static unsigned long magician_pin_config[] __initdata = { GPIO107_GPIO, /* DS1WM_IRQ */ GPIO108_GPIO, /* GSM_READY */ GPIO115_GPIO, /* nPEN_IRQ */ + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, }; /* diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f2c7ad8..5f22496 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -128,6 +128,10 @@ static unsigned long mainstone_pin_config[] = { GPIO108_KP_MKOUT_5, GPIO96_KP_MKOUT_6, + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + /* GPIO */ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, }; diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 2061c00..33626de 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -38,12 +38,13 @@ struct gpio_desc { unsigned valid : 1; unsigned can_wakeup : 1; unsigned keypad_gpio : 1; + unsigned dir_inverted : 1; unsigned int mask; /* bit mask in PWER or PKWR */ + unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */ unsigned long config; }; static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; -static int gpio_nr; static unsigned long gpdr_lpm[4]; @@ -54,7 +55,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ int shft = (gpio & 0xf) << 1; int fn = MFP_AF(c); - int dir = c & MFP_DIR_OUT; + int is_out = (c & MFP_DIR_OUT) ? 1 : 0; if (fn > 3) return -EINVAL; @@ -68,7 +69,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) else GAFR_U(bank) = gafr; - if (dir == MFP_DIR_OUT) + if (is_out ^ gpio_desc[gpio].dir_inverted) GPDR(gpio) |= mask; else GPDR(gpio) &= ~mask; @@ -77,11 +78,11 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) switch (c & MFP_LPM_STATE_MASK) { case MFP_LPM_DRIVE_HIGH: PGSR(bank) |= mask; - dir = MFP_DIR_OUT; + is_out = 1; break; case MFP_LPM_DRIVE_LOW: PGSR(bank) &= ~mask; - dir = MFP_DIR_OUT; + is_out = 1; break; case MFP_LPM_DEFAULT: break; @@ -92,7 +93,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) break; } - if (dir == MFP_DIR_OUT) + if (is_out ^ gpio_desc[gpio].dir_inverted) gpdr_lpm[bank] |= mask; else gpdr_lpm[bank] &= ~mask; @@ -106,7 +107,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) return -EINVAL; } - if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) { + if ((c & MFP_LPM_CAN_WAKEUP) && is_out) { pr_warning("%s: output GPIO%d unable to wakeup\n", __func__, gpio); return -EINVAL; @@ -169,7 +170,7 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm) int gpio_set_wake(unsigned int gpio, unsigned int on) { struct gpio_desc *d; - unsigned long c; + unsigned long c, mux_taken; if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) return -EINVAL; @@ -183,9 +184,13 @@ int gpio_set_wake(unsigned int gpio, unsigned int on) if (d->keypad_gpio) return -EINVAL; + mux_taken = (PWER & d->mux_mask) & (~d->mask); + if (on && mux_taken) + return -EBUSY; + if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { if (on) { - PWER |= d->mask; + PWER = (PWER & ~d->mux_mask) | d->mask; if (c & MFP_LPM_EDGE_RISE) PRER |= d->mask; @@ -210,7 +215,7 @@ static void __init pxa25x_mfp_init(void) { int i; - for (i = 0; i <= 84; i++) + for (i = 0; i <= pxa_last_gpio; i++) gpio_desc[i].valid = 1; for (i = 0; i <= 15; i++) { @@ -218,7 +223,11 @@ static void __init pxa25x_mfp_init(void) gpio_desc[i].mask = GPIO_bit(i); } - gpio_nr = 85; + /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the + * direction bit inverted in GPDR2. See PXA26x DM 4.1.1. + */ + for (i = 86; i <= pxa_last_gpio; i++) + gpio_desc[i].dir_inverted = 1; } #else static inline void pxa25x_mfp_init(void) {} @@ -251,11 +260,27 @@ int keypad_set_wake(unsigned int on) return 0; } +#define PWER_WEMUX2_GPIO38 (1 << 16) +#define PWER_WEMUX2_GPIO53 (2 << 16) +#define PWER_WEMUX2_GPIO40 (3 << 16) +#define PWER_WEMUX2_GPIO36 (4 << 16) +#define PWER_WEMUX2_MASK (7 << 16) +#define PWER_WEMUX3_GPIO31 (1 << 19) +#define PWER_WEMUX3_GPIO113 (2 << 19) +#define PWER_WEMUX3_MASK (3 << 19) + +#define INIT_GPIO_DESC_MUXED(mux, gpio) \ +do { \ + gpio_desc[(gpio)].can_wakeup = 1; \ + gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \ + gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \ +} while (0) + static void __init pxa27x_mfp_init(void) { int i, gpio; - for (i = 0; i <= 120; i++) { + for (i = 0; i <= pxa_last_gpio; i++) { /* skip GPIO2, 5, 6, 7, 8, they are not * valid pins allow configuration */ @@ -286,7 +311,12 @@ static void __init pxa27x_mfp_init(void) gpio_desc[35].can_wakeup = 1; gpio_desc[35].mask = PWER_WE35; - gpio_nr = 121; + INIT_GPIO_DESC_MUXED(WEMUX3, 31); + INIT_GPIO_DESC_MUXED(WEMUX3, 113); + INIT_GPIO_DESC_MUXED(WEMUX2, 38); + INIT_GPIO_DESC_MUXED(WEMUX2, 53); + INIT_GPIO_DESC_MUXED(WEMUX2, 40); + INIT_GPIO_DESC_MUXED(WEMUX2, 36); } #else static inline void pxa27x_mfp_init(void) {} @@ -300,7 +330,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) { int i; - for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); @@ -315,7 +345,7 @@ static int pxa2xx_mfp_resume(struct sys_device *d) { int i; - for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; GPDR(i * 32) = saved_gpdr[i]; @@ -348,7 +378,7 @@ static int __init pxa2xx_mfp_init(void) pxa27x_mfp_init(); /* initialize gafr_run[], pgsr_lpm[] from existing values */ - for (i = 0; i <= gpio_to_bank(gpio_nr); i++) + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); return sysdev_class_register(&pxa2xx_mfp_sysclass); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 782903f..2b427e0 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -34,7 +34,7 @@ #include <linux/irq.h> #include <linux/pda_power.h> #include <linux/power_supply.h> -#include <linux/wm97xx.h> +#include <linux/wm97xx_batt.h> #include <linux/mtd/physmap.h> #include <asm/mach-types.h> @@ -46,6 +46,9 @@ #include <mach/mmc.h> #include <mach/udc.h> #include <mach/pxa27x-udc.h> +#include <mach/i2c.h> +#include <mach/camera.h> +#include <media/soc_camera.h> #include <mach/mioa701.h> @@ -54,10 +57,11 @@ static unsigned long mioa701_pin_config[] = { /* Mio global */ - MIO_CFG_OUT(GPIO9_CHARGE_nEN, AF0, DRIVE_LOW), + MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW), MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW), MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH), MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH), + MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0), /* Backlight PWM 0 */ GPIO16_PWM0_OUT, @@ -74,7 +78,7 @@ static unsigned long mioa701_pin_config[] = { MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), /* USB */ - MIO_CFG_IN(GPIO13_USB_DETECT, AF0), + MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0), MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), /* LCD */ @@ -98,12 +102,29 @@ static unsigned long mioa701_pin_config[] = { GPIO75_LCD_LCLK, GPIO76_LCD_PCLK, + /* QCI */ + GPIO12_CIF_DD_7, + GPIO17_CIF_DD_6, + GPIO50_CIF_DD_3, + GPIO51_CIF_DD_2, + GPIO52_CIF_DD_4, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO55_CIF_DD_1, + GPIO81_CIF_DD_0, + GPIO82_CIF_DD_5, + GPIO84_CIF_FV, + GPIO85_CIF_LV, + /* Bluetooth */ + MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0), GPIO44_BTUART_CTS, GPIO42_BTUART_RXD, GPIO45_BTUART_RTS, GPIO43_BTUART_TXD, MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW), + MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH), + MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH), /* GPS */ MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW), @@ -151,16 +172,16 @@ static unsigned long mioa701_pin_config[] = { GPIO104_KP_MKOUT_1, GPIO105_KP_MKOUT_2, + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + /* Unknown */ - MFP_CFG_IN(GPIO14, AF0), MFP_CFG_IN(GPIO20, AF0), MFP_CFG_IN(GPIO21, AF0), MFP_CFG_IN(GPIO33, AF0), MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH), MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH), - MFP_CFG_OUT(GPIO77, AF0, DRIVE_HIGH), - MFP_CFG_IN(GPIO80, AF0), - MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH), MFP_CFG_IN(GPIO96, AF0), MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH), }; @@ -407,7 +428,7 @@ static void udc_power_command(int cmd) static int is_usb_connected(void) { - return !!gpio_get_value(GPIO13_USB_DETECT); + return !gpio_get_value(GPIO13_nUSB_DETECT); } static struct pxa2xx_udc_mach_info mioa701_udc_info = { @@ -659,13 +680,19 @@ static char *supplicants[] = { "mioa701_battery" }; +static int is_ac_connected(void) +{ + return gpio_get_value(GPIO96_AC_DETECT); +} + static void mioa701_set_charge(int flags) { - gpio_set_value(GPIO9_CHARGE_nEN, !flags); + gpio_set_value(GPIO9_CHARGE_EN, (flags == PDA_POWER_CHARGE_USB)); } static struct pda_power_pdata power_pdata = { - .is_ac_online = is_usb_connected, + .is_ac_online = is_ac_connected, + .is_usb_online = is_usb_connected, .set_charge = mioa701_set_charge, .supplied_to = supplicants, .num_supplicants = ARRAY_SIZE(supplicants), @@ -674,8 +701,15 @@ static struct pda_power_pdata power_pdata = { static struct resource power_resources[] = { [0] = { .name = "ac", - .start = gpio_to_irq(GPIO13_USB_DETECT), - .end = gpio_to_irq(GPIO13_USB_DETECT), + .start = gpio_to_irq(GPIO96_AC_DETECT), + .end = gpio_to_irq(GPIO96_AC_DETECT), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | + IORESOURCE_IRQ_LOWEDGE, + }, + [1] = { + .name = "usb", + .start = gpio_to_irq(GPIO13_nUSB_DETECT), + .end = gpio_to_irq(GPIO13_nUSB_DETECT), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, }, @@ -691,120 +725,43 @@ static struct platform_device power_dev = { }, }; -#if defined(CONFIG_PDA_POWER) && defined(CONFIG_TOUCHSCREEN_WM97XX) -static struct wm97xx *battery_wm; - -static enum power_supply_property battery_props[] = { - POWER_SUPPLY_PROP_STATUS, - POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, - POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, - POWER_SUPPLY_PROP_VOLTAGE_NOW, - POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, /* Necessary for apm */ +static struct wm97xx_batt_info mioa701_battery_data = { + .batt_aux = WM97XX_AUX_ID1, + .temp_aux = -1, + .charge_gpio = -1, + .min_voltage = 0xc00, + .max_voltage = 0xfc0, + .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, + .batt_div = 1, + .batt_mult = 1, + .batt_name = "mioa701_battery", }; -static int get_battery_voltage(void) -{ - int adc = -1; - - if (battery_wm) - adc = wm97xx_read_aux_adc(battery_wm, WM97XX_AUX_ID1); - return adc; -} - -static int get_battery_status(struct power_supply *b) -{ - int status; - - if (is_usb_connected()) - status = POWER_SUPPLY_STATUS_CHARGING; - else - status = POWER_SUPPLY_STATUS_DISCHARGING; - - return status; -} - -static int get_property(struct power_supply *b, - enum power_supply_property psp, - union power_supply_propval *val) -{ - int rc = 0; - - switch (psp) { - case POWER_SUPPLY_PROP_STATUS: - val->intval = get_battery_status(b); - break; - case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: - val->intval = 0xfd0; - break; - case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: - val->intval = 0xc00; - break; - case POWER_SUPPLY_PROP_VOLTAGE_NOW: - val->intval = get_battery_voltage(); - break; - case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: - val->intval = 100; - break; - default: - val->intval = -1; - rc = -1; - } - - return rc; +/* + * Camera interface + */ +struct pxacamera_platform_data mioa701_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 5000, }; -static struct power_supply battery_ps = { - .name = "mioa701_battery", - .type = POWER_SUPPLY_TYPE_BATTERY, - .get_property = get_property, - .properties = battery_props, - .num_properties = ARRAY_SIZE(battery_props), +static struct soc_camera_link iclink = { + .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ }; -static int battery_probe(struct platform_device *pdev) -{ - struct wm97xx *wm = platform_get_drvdata(pdev); - int rc; - - battery_wm = wm; - - rc = power_supply_register(NULL, &battery_ps); - if (rc) - dev_err(&pdev->dev, - "Could not register mioa701 battery -> %d\n", rc); - return rc; -} - -static int battery_remove(struct platform_device *pdev) -{ - battery_wm = NULL; - return 0; -} - -static struct platform_driver mioa701_battery_driver = { - .driver = { - .name = "wm97xx-battery", +/* Board I2C devices. */ +static struct i2c_board_info __initdata mioa701_i2c_devices[] = { + { + /* Must initialize before the camera(s) */ + I2C_BOARD_INFO("mt9m111", 0x5d), + .platform_data = &iclink, }, - .probe = battery_probe, - .remove = battery_remove }; -static int __init mioa701_battery_init(void) -{ - int rc; - - rc = platform_driver_register(&mioa701_battery_driver); - if (rc) - printk(KERN_ERR "Could not register mioa701 battery driver\n"); - return rc; -} - -#else -static int __init mioa701_battery_init(void) -{ - return 0; -} -#endif +struct i2c_pxa_platform_data i2c_pdata = { + .fast_mode = 1, +}; /* * Mio global @@ -851,17 +808,17 @@ static void mioa701_machine_exit(void); static void mioa701_poweroff(void) { mioa701_machine_exit(); - gpio_set_value(GPIO18_POWEROFF, 1); + arm_machine_restart('s'); } static void mioa701_restart(char c) { mioa701_machine_exit(); - arm_machine_restart(c); + arm_machine_restart('s'); } struct gpio_ress global_gpios[] = { - MIO_GPIO_OUT(GPIO9_CHARGE_nEN, 1, "Charger enable"), + MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"), MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"), MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power") }; @@ -879,12 +836,16 @@ static void __init mioa701_machine_init(void) set_pxa_fb_info(&mioa701_pxafb_info); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); + wm97xx_bat_set_pdata(&mioa701_battery_data); udc_init(); pm_power_off = mioa701_poweroff; arm_pm_restart = mioa701_restart; platform_add_devices(devices, ARRAY_SIZE(devices)); gsm_init(); - mioa701_battery_init(); + + pxa_set_i2c_info(&i2c_pdata); + pxa_set_camera_info(&mioa701_pxacamera_platform_data); + i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); } static void mioa701_machine_exit(void) diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index f601425..1e75154 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -55,6 +55,10 @@ static unsigned long pcm990_pin_config[] __initdata = { GPIO89_USBH1_PEN, /* PWM0 */ GPIO16_PWM0_OUT, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, }; /* diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 2e3bd8b..ae88855 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -20,6 +20,7 @@ #include <linux/fb.h> #include <linux/pm.h> #include <linux/delay.h> +#include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -413,9 +414,40 @@ static struct pxafb_mach_info poodle_fb_info = { .lcd_conn = LCD_COLOR_TFT_16BPP, }; +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00120000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &poodle_locomo_device, &poodle_scoop_device, + &sharpsl_rom_device, }; static void poodle_poweroff(void) diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 344b328..6c57522 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -36,12 +36,6 @@ #include "devices.h" #include "clock.h" -int cpu_is_pxa26x(void) -{ - return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0); -} -EXPORT_SYMBOL_GPL(cpu_is_pxa26x); - /* * Various clock factors driven by the CCCR register. */ @@ -319,13 +313,21 @@ void __init pxa25x_init_irq(void) pxa_init_gpio(85, pxa25x_set_wake); } +#ifdef CONFIG_CPU_PXA26x +void __init pxa26x_init_irq(void) +{ + pxa_init_irq(32, pxa25x_set_wake); + pxa_init_gpio(90, pxa25x_set_wake); +} +#endif + static struct platform_device *pxa25x_devices[] __initdata = { &pxa25x_device_udc, &pxa_device_ffuart, &pxa_device_btuart, &pxa_device_stuart, &pxa_device_i2s, - &pxa_device_rtc, + &sa1100_device_rtc, &pxa25x_device_ssp, &pxa25x_device_nssp, &pxa25x_device_assp, @@ -371,7 +373,7 @@ static int __init pxa25x_init(void) } /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ - if (cpu_is_pxa255() || cpu_is_pxa26x()) { + if (cpu_is_pxa255()) { clks_register(&pxa25x_hwuart_clkreg, 1); ret = platform_device_register(&pxa_device_hwuart); } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 15c8e5b..411bec5 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -332,38 +332,18 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on) void __init pxa27x_init_irq(void) { pxa_init_irq(34, pxa27x_set_wake); - pxa_init_gpio(128, pxa27x_set_wake); + pxa_init_gpio(121, pxa27x_set_wake); } /* * device registration specific to PXA27x. */ - -static struct resource i2c_power_resources[] = { - { - .start = 0x40f00180, - .end = 0x40f001a3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PWRI2C, - .end = IRQ_PWRI2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa27x_device_i2c_power = { - .name = "pxa2xx-i2c", - .id = 1, - .resource = i2c_power_resources, - .num_resources = ARRAY_SIZE(i2c_power_resources), -}; - void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) { local_irq_disable(); PCFR |= PCFR_PI2CEN; local_irq_enable(); - pxa27x_device_i2c_power.dev.platform_data = info; + pxa_register_device(&pxa27x_device_i2c_power, info); } static struct platform_device *devices[] __initdata = { @@ -372,8 +352,8 @@ static struct platform_device *devices[] __initdata = { &pxa_device_btuart, &pxa_device_stuart, &pxa_device_i2s, + &sa1100_device_rtc, &pxa_device_rtc, - &pxa27x_device_i2c_power, &pxa27x_device_ssp1, &pxa27x_device_ssp2, &pxa27x_device_ssp3, diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index b7e5382..4908938 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -29,6 +29,7 @@ #include <mach/pm.h> #include <mach/dma.h> #include <mach/ssp.h> +#include <mach/i2c.h> #include "generic.h" #include "devices.h" @@ -544,28 +545,9 @@ void __init pxa3xx_init_irq(void) * device registration specific to PXA3xx. */ -static struct resource i2c_power_resources[] = { - { - .start = 0x40f500c0, - .end = 0x40f500d3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PWRI2C, - .end = IRQ_PWRI2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa3xx_device_i2c_power = { - .name = "pxa2xx-i2c", - .id = 1, - .resource = i2c_power_resources, - .num_resources = ARRAY_SIZE(i2c_power_resources), -}; - void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) { - pxa3xx_device_i2c_power.dev.platform_data = info; + pxa_register_device(&pxa3xx_device_i2c_power, info); } static struct platform_device *devices[] __initdata = { @@ -574,6 +556,7 @@ static struct platform_device *devices[] __initdata = { &pxa_device_btuart, &pxa_device_stuart, &pxa_device_i2s, + &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, &pxa27x_device_ssp2, @@ -581,7 +564,6 @@ static struct platform_device *devices[] __initdata = { &pxa3xx_device_ssp4, &pxa27x_device_pwm0, &pxa27x_device_pwm1, - &pxa3xx_device_i2c_power, }; static struct sys_device pxa3xx_sysdev[] = { diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 3be76ee..7299d87 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -22,6 +22,7 @@ #include <linux/gpio.h> #include <linux/leds.h> #include <linux/mmc/host.h> +#include <linux/mtd/physmap.h> #include <linux/pm.h> #include <linux/backlight.h> #include <linux/io.h> @@ -122,6 +123,10 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */ GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */ + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, }; @@ -609,10 +614,41 @@ static struct pxafb_mach_info spitz_pxafb_info = { }; +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00140000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &spitzscoop_device, &spitzkbd_device, &spitzled_device, + &sharpsl_rom_device, }; static void spitz_poweroff(void) diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 224897a..3332e5d 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -25,6 +25,7 @@ #include <linux/mfd/tmio.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/pm.h> #include <linux/gpio_keys.h> #include <linux/input.h> @@ -733,6 +734,45 @@ static void tosa_tc6393xb_teardown(struct platform_device *dev) gpio_free(TOSA_GPIO_CARD_VCC_ON); } +#ifdef CONFIG_MFD_TC6393XB +static struct fb_videomode tosa_tc6393xb_lcd_mode[] = { + { + .xres = 480, + .yres = 640, + .pixclock = 0x002cdf00,/* PLL divisor */ + .left_margin = 0x004c, + .right_margin = 0x005b, + .upper_margin = 0x0001, + .lower_margin = 0x000d, + .hsync_len = 0x0002, + .vsync_len = 0x0001, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + },{ + .xres = 240, + .yres = 320, + .pixclock = 0x00e7f203,/* PLL divisor */ + .left_margin = 0x0024, + .right_margin = 0x002f, + .upper_margin = 0x0001, + .lower_margin = 0x000d, + .hsync_len = 0x0002, + .vsync_len = 0x0001, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + } +}; + +static struct tmio_fb_data tosa_tc6393xb_fb_config = { + .lcd_set_power = tc6393xb_lcd_set_power, + .lcd_mode = tc6393xb_lcd_mode, + .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode), + .modes = &tosa_tc6393xb_lcd_mode[0], + .height = 82, + .width = 60, +}; +#endif + static struct tc6393xb_platform_data tosa_tc6393xb_data = { .scr_pll2cr = 0x0cc1, .scr_gper = 0x3300, @@ -748,6 +788,9 @@ static struct tc6393xb_platform_data tosa_tc6393xb_data = { .resume = tosa_tc6393xb_resume, .nand_data = &tosa_tc6393xb_nand_config, +#ifdef CONFIG_MFD_TC6393XB + .fb_data = &tosa_tc6393xb_fb_config, +#endif .resume_restore = 1, }; @@ -789,6 +832,36 @@ static struct spi_board_info spi_board_info[] __initdata = { }, }; +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00160000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &tosascoop_device, &tosascoop_jc_device, @@ -798,6 +871,7 @@ static struct platform_device *devices[] __initdata = { &tosa_gpio_keys_device, &tosaled_device, &tosa_bt_device, + &sharpsl_rom_device, }; static void tosa_poweroff(void) diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 8138044..218d200 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -18,6 +18,7 @@ #include <linux/interrupt.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/gpio.h> #include <linux/pwm_backlight.h> #include <linux/smc91x.h> @@ -25,7 +26,6 @@ #include <asm/mach/arch.h> #include <mach/hardware.h> #include <mach/audio.h> -#include <mach/gpio.h> #include <mach/pxafb.h> #include <mach/zylonite.h> #include <mach/mmc.h> diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 0f24474..28e4e62 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -16,8 +16,8 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> +#include <linux/gpio.h> -#include <mach/gpio.h> #include <mach/mfp-pxa320.h> #include <mach/zylonite.h> |
