diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-07 20:55:16 +0900 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-07 20:55:16 +0900 |
| commit | 5e090ed7af10729a396a25df43d69a236e789736 (patch) | |
| tree | 09ba2dd9974b5224721fbc413bcf6ac9b2ac73f9 /arch/arm/mach-omap2 | |
| parent | 84424026c0a910886064049d414a12a4f4dd125e (diff) | |
| parent | 54d69df5849ec2e660aa12ac75562618c10fb499 (diff) | |
| download | op-kernel-dev-5e090ed7af10729a396a25df43d69a236e789736.zip op-kernel-dev-5e090ed7af10729a396a25df43d69a236e789736.tar.gz | |
Merge tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull late ARM soc platform updates from Olof Johansson:
"This branch contains updates to OMAP and Marvell platforms (kirkwood,
dove, mvebu) that came in after we had done the big multiplatform
merges, so they were kept separate from the rest, and not separated
into the traditional topics of cleanup/driver/platform features.
For OMAP, the updates are:
- Runtime PM conversions for the GPMC and RNG IP blocks
- Preparation patches for the OMAP common clock framework conversion
- clkdev alias additions required by other drivers
- Performance Monitoring Unit (PMU) support for OMAP2, 3, and
non-4430 OMAP4
- OMAP hwmod code and data improvements
- Preparation patches for the IOMMU runtime PM conversion
- Preparation patches for OMAP4 full-chip retention support
For Kirkwood/Dove/mvebu:
- New driver for "address decoder controller" for mvebu, which is a
piece of hardware that configures addressable devices and
peripherals. First user is the boot rom aperture on armada XP
since it is needed for SMP support.
- New device tree bindings for peripherals such as gpio-fan, iconnect
nand, mv_cesa and the above address decoder controller.
- Some defconfig updates, mostly to enable new DT boards and a few
drivers.
- New drivers using the pincontrol subsystem for dove, kirkwood and
mvebu
- New clean gpio driver for mvebu"
* tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits)
ARM: mvebu: fix build breaks from multi-platform conversion
ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70
ARM: OMAP2+: PMU: Add runtime PM support
ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD
ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD
ARM: OMAP3: hwmod data: Add debugss HWMOD data
ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
hwrng: OMAP: remove SoC restrictions from driver registration
ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
hwrng: OMAP: convert to use runtime PM
hwrng: OMAP: store per-device data in per-device variables, not file statics
ARM: OMAP2xxx: hwmod/CM: add RNG integration data
ARM: OMAP2+: gpmc: minimal driver support
ARM: OMAP2+: gpmc: Adapt to HWMOD
ARM: OMAP2/3: hwmod data: add gpmc
ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp
ARM: OMAP3: hwmod data: add mmu data for iva and isp
ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected
ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks
...
Diffstat (limited to 'arch/arm/mach-omap2')
44 files changed, 1911 insertions, 331 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 7d6abda..fe40d9e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -179,6 +179,7 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o +obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 3e2d76f..cea3aba 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void) return; } - clk_enable(gpmc_fck); + clk_prepare_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); eth_cs = APOLLON_ETH_CS; @@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void) gpmc_cs_free(APOLLON_ETH_CS); } out: - clk_disable(gpmc_fck); + clk_disable_unprepare(gpmc_fck); clk_put(gpmc_fck); } diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index f6c48dd..8d04bf8 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void) return; } - clk_enable(gpmc_fck); + clk_prepare_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); - clk_disable(gpmc_fck); + clk_disable_unprepare(gpmc_fck); clk_put(gpmc_fck); if (is_gpmc_muxed()) @@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void) gpmc_cs_free(eth_cs); out: - clk_disable(gpmc_fck); + clk_disable_unprepare(gpmc_fck); clk_put(gpmc_fck); } diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index e0dd70b..2b012f9 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void) return; } clk_set_rate(phy_ref_clk, 19200000); - clk_enable(phy_ref_clk); + clk_prepare_enable(phy_ref_clk); /* disable the power to the usb hub prior to init and reset phy+hub */ ret = gpio_request_array(panda_ehci_gpios, diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index b19a1f7..c2d1521 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, - OMAP24XX_CM_IDLEST_VAL, clk->name); + OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); /* * REVISIT: Should we return an error code if omap2_wait_clock_ready() diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index cabcfdb..3524f0e7 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) { const struct prcm_config *ptr; - long highest_rate; + long highest_rate, sys_clk_rate; highest_rate = -EINVAL; + sys_clk_rate = __clk_get_rate(sclk); for (ptr = rate_table; ptr->mpu_speed; ptr++) { if (!(ptr->flags & cpu_mask)) continue; - if (ptr->xtal_speed != sclk->rate) + if (ptr->xtal_speed != sys_clk_rate) continue; highest_rate = ptr->mpu_speed; @@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) const struct prcm_config *prcm; unsigned long found_speed = 0; unsigned long flags; + long sys_clk_rate; + + sys_clk_rate = __clk_get_rate(sclk); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; - if (prcm->xtal_speed != sclk->rate) + if (prcm->xtal_speed != sys_clk_rate) continue; if (prcm->mpu_speed <= rate) { diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 298887b..7c6da2f 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; + unsigned long clkrate; if (!clk || !rate) return -EINVAL; @@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (validrate != rate) return -EINVAL; - sdrcrate = sdrc_ick_p->rate; - if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) >> 1); + sdrcrate = __clk_get_rate(sdrc_ick_p); + clkrate = __clk_get_rate(clk); + if (rate > clkrate) + sdrcrate <<= ((rate / clkrate) >> 1); else - sdrcrate >>= ((clk->rate / rate) >> 1); + sdrcrate >>= ((clkrate / rate) >> 1); ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); if (ret) @@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; + _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS; @@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (c == 0) c = 1; - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, - validrate); + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", + clkrate, validrate); pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); @@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (sdrc_cs1) omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); else omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 19a9809..eaed390 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", - clk->name, src_clk->name); + __clk_get_name(clk), __clk_get_name(src_clk)); return NULL; } @@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, if (max_div == 0) { /* This indicates an error in the clksel data */ WARN(1, "clock: %s: could not find divisor for parent %s\n", - clk->name, src_clk->parent->name); + __clk_get_name(clk), + __clk_get_name(__clk_get_parent(src_clk))); return 0; } @@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; + struct clk *parent; - clks = _get_clksel_by_parent(clk, clk->parent); + parent = __clk_get_parent(clk); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return 0; @@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ - WARN(1, "clock: %s: could not find fieldval %d parent %s\n", - clk->name, field_val, clk->parent->name); + WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", + __clk_get_name(clk), field_val, __clk_get_name(parent)); return 0; } @@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; + struct clk *parent; /* should never happen */ WARN_ON(div == 0); - clks = _get_clksel_by_parent(clk, clk->parent); + parent = __clk_get_parent(clk); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) } if (!clkr->div) { - pr_err("clock: %s: could not find divisor %d parent %s\n", - clk->name, div, clk->parent->name); + pr_err("clock: %s: could not find divisor %d for parent %s\n", + __clk_get_name(clk), div, __clk_get_name(parent)); return ~0; } @@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; + struct clk *parent; + unsigned long parent_rate; + const char *clk_name; + + parent = __clk_get_parent(clk); + parent_rate = __clk_get_rate(parent); + clk_name = __clk_get_name(clk); if (!clk->clksel || !clk->clksel_mask) return ~0; pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); + clk_name, target_rate); *new_div = 1; - clks = _get_clksel_by_parent(clk, clk->parent); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - pr_err("clock: %s: clksel_rate table not sorted", - clk->name); + pr_err("clock: %s: clksel_rate table not sorted\n", + clk_name); last_div = clkr->div; - test_rate = clk->parent->rate / clkr->div; + test_rate = parent_rate / clkr->div; if (test_rate <= target_rate) break; /* found it */ } if (!clkr->div) { - pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n", - clk->name, target_rate, clk->parent->name); + pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n", + clk_name, target_rate, __clk_get_name(parent)); return ~0; } *new_div = clkr->div; pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + (parent_rate / clkr->div)); - return clk->parent->rate / clkr->div; + return parent_rate / clkr->div; } /* @@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk) const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; + struct clk *parent; + const char *clk_name; if (!clk->clksel || !clk->clksel_mask) return; + parent = __clk_get_parent(clk); + clk_name = __clk_get_name(clk); + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; r >>= __ffs(clk->clksel_mask); @@ -357,11 +374,13 @@ void omap2_init_clksel_parent(struct clk *clk) continue; if (clkr->val == r) { - if (clk->parent != clks->parent) { + if (parent != clks->parent) { pr_debug("clock: %s: inited parent to %s (was %s)\n", - clk->name, clks->parent->name, - ((clk->parent) ? - clk->parent->name : "NULL")); + clk_name, + __clk_get_name(clks->parent), + ((parent) ? + __clk_get_name(parent) : + "NULL")); clk_reparent(clk, clks->parent); }; found = 1; @@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk) /* This indicates a data error */ WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk->name, r); + clk_name, r); return; } @@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk) { unsigned long rate; u32 div = 0; + struct clk *parent; div = _read_divisor(clk); if (div == 0) - return clk->rate; + return __clk_get_rate(clk); - rate = clk->parent->rate / div; + parent = __clk_get_parent(clk); + rate = __clk_get_rate(parent) / div; - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, - rate, div); + pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", + __clk_get_name(clk), rate, div); return rate; } @@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); - clk->rate = clk->parent->rate / new_div; + clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; - pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), + __clk_get_rate(clk)); return 0; } @@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) clk_reparent(clk, new_parent); /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = new_parent->rate; + clk->rate = __clk_get_rate(new_parent); if (parent_div > 0) - clk->rate /= parent_div; + __clk_get_rate(clk) /= parent_div; pr_debug("clock: %s: set parent to %s (new rate %ld)\n", - clk->name, clk->parent->name, clk->rate); + __clk_get_name(clk), + __clk_get_name(__clk_get_parent(clk)), + __clk_get_rate(clk)); return 0; } diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 83b658b..8041114 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ - fint = clk->parent->rate / n; + fint = __clk_get_rate(__clk_get_parent(clk)) / n; if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; + return __clk_get_rate(dd->clk_bypass); } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; + return __clk_get_rate(dd->clk_bypass); } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) - return dd->clk_bypass->rate; + return __clk_get_rate(dd->clk_bypass); } v = __raw_readl(dd->mult_div1_reg); @@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) dpll_div = v & dd->div1_mask; dpll_div >>= __ffs(dd->div1_mask); - dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; + dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult; do_div(dpll_clk, dpll_div + 1); return dpll_clk; @@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) unsigned long scaled_rt_rp; unsigned long new_rate = 0; struct dpll_data *dd; + unsigned long ref_rate; + const char *clk_name; if (!clk || !clk->dpll_data) return ~0; dd = clk->dpll_data; + ref_rate = __clk_get_rate(dd->clk_ref); + clk_name = __clk_get_name(clk); pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", - clk->name, target_rate); + clk_name, target_rate); - scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); + scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; dd->last_rounded_rate = 0; @@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) break; r = _dpll_test_mult(&m, n, &new_rate, target_rate, - dd->clk_ref->rate); + ref_rate); /* m can't be set low enough for this n - try with a larger n */ if (r == DPLL_MULT_UNDERFLOW) continue; pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", - clk->name, m, n, new_rate); + clk_name, m, n, new_rate); if (target_rate == new_rate) { dd->last_rounded_m = m; @@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) } if (target_rate != new_rate) { - pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, - target_rate); + pr_debug("clock: %s: cannot round to rate %ld\n", + clk_name, target_rate); return ~0; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e97f98f..961ac8f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk) clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, - clk->name); + __clk_get_name(clk)); } /* Public functions */ @@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk) void omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; + const char *clk_name; if (!clk->clkdm_name) return; + clk_name = __clk_get_name(clk); + clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { pr_debug("clock: associated clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); + clk_name, clk->clkdm_name); clk->clkdm = clkdm; } else { pr_debug("clock: could not associate clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); + clk_name, clk->clkdm_name); } } diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 12c178d..c3cde1a 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK(NULL, "dss_ick", &dss_ick, CK_242X), CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), @@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), @@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), CLK("omap24xxcam", "fck", &cam_fck, CK_242X), + CLK(NULL, "cam_fck", &cam_fck, CK_242X), CLK("omap24xxcam", "ick", &cam_ick, CK_242X), + CLK(NULL, "cam_ick", &cam_ick, CK_242X), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), @@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), CLK(NULL, "fac_ick", &fac_ick, CK_242X), CLK(NULL, "fac_fck", &fac_fck, CK_242X), CLK(NULL, "eac_ick", &eac_ick, CK_242X), CLK(NULL, "eac_fck", &eac_fck, CK_242X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), @@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), + CLK(NULL, "rng_ick", &rng_ick, CK_242X), CLK("omap-aes", "ick", &aes_ick, CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb-hdrc", "fck", &osc_ck, CK_242X), - CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), - CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), }; /* diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 7ea9139..22404fe 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK(NULL, "dss_ick", &dss_ick, CK_243X), CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), @@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), @@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), CLK(NULL, "icr_ick", &icr_ick, CK_243X), CLK("omap24xxcam", "fck", &cam_fck, CK_243X), + CLK(NULL, "cam_fck", &cam_fck, CK_243X), CLK("omap24xxcam", "ick", &cam_ick, CK_243X), + CLK(NULL, "cam_ick", &cam_ick, CK_243X), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), @@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "fac_ick", &fac_ick, CK_243X), CLK(NULL, "fac_fck", &fac_fck, CK_243X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), @@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), + CLK(NULL, "rng_ick", &rng_ick, CK_243X), CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index 2026311..b87b88c 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), + CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 15cdc647..83bb014 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void) dpll5_clk = clk_get(NULL, "dpll5_ck"); clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_enable(dpll5_clk); + clk_prepare_enable(dpll5_clk); /* Program dpll5_m2_clk divider for no division */ dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_enable(dpll5_m2_clk); + clk_prepare_enable(dpll5_m2_clk); clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - clk_disable(dpll5_m2_clk); - clk_disable(dpll5_clk); + clk_disable_unprepare(dpll5_m2_clk); + clk_disable_unprepare(dpll5_clk); return; } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 700317a..1f42c9d 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = { * clkdev */ -/* XXX At some point we should rename this file to clock3xxx_data.c */ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), @@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), + CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), + CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX), CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), @@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), + CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), @@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), + CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), @@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), @@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), + CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), @@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), @@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), + CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), + CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), + CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), @@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), + CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), @@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), @@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), + CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), @@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), + CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), + CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), + CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), @@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), + CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), + CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), + CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX), + CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX), CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), @@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), + CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), }; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 500682c..d661d13 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_fck", &dss_fck, CK_443X), CLK("omapdss_dss", "ick", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), @@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "rng_ick", &rng_ick, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), @@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), @@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), @@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), @@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), }; int __init omap4xxx_clk_init(void) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a155562..cbb8791 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -899,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm) return ret; } +/** + * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use? + * @clkdm: struct clockdomain * + * + * Returns true if clockdomain @clkdm has the + * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is + * null. More information is available in the documentation for the + * CLKDM_MISSING_IDLE_REPORTING macro. + */ +bool clkdm_missing_idle_reporting(struct clockdomain *clkdm) +{ + if (!clkdm) + return false; + + return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false; +} + /* Clockdomain-to-clock/hwmod framework interface code */ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 5601dc1..629576b 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -1,9 +1,7 @@ /* - * arch/arm/plat-omap/include/mach/clockdomain.h - * * OMAP2/3 clockdomain framework functions * - * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008, 2012 Texas Instruments, Inc. * Copyright (C) 2008-2011 Nokia Corporation * * Paul Walmsley @@ -34,6 +32,20 @@ * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is * active whenever the MPU is active. True for interconnects and * the WKUP clockdomains. + * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and + * clocks inside this clockdomain are not taken into account by + * the PRCM when determining whether the clockdomain is idle. + * Without this flag, if the clockdomain is set to + * hardware-supervised idle mode, the PRCM may transition the + * enclosing powerdomain to a low power state, even when devices + * inside the clockdomain and powerdomain are in use. (An example + * of such a clockdomain is the EMU clockdomain on OMAP3/4.) If + * this flag is set, and the clockdomain does not support the + * force-sleep mode, then the HW_AUTO mode will be used to put the + * clockdomain to sleep. Similarly, if the clockdomain supports + * the force-wakeup mode, then it will be used whenever a clock or + * IP block inside the clockdomain is active, rather than the + * HW_AUTO mode. */ #define CLKDM_CAN_FORCE_SLEEP (1 << 0) #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) @@ -41,6 +53,7 @@ #define CLKDM_CAN_DISABLE_AUTO (1 << 3) #define CLKDM_NO_AUTODEPS (1 << 4) #define CLKDM_ACTIVE_WITH_MPU (1 << 5) +#define CLKDM_MISSING_IDLE_REPORTING (1 << 6) #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) @@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); void clkdm_allow_idle(struct clockdomain *clkdm); void clkdm_deny_idle(struct clockdomain *clkdm); bool clkdm_in_hwsup(struct clockdomain *clkdm); +bool clkdm_missing_idle_reporting(struct clockdomain *clkdm); int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index f99e65c..9a7792a 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm) clkdm->clktrctrl_mask); } +static int omap3_clkdm_sleep(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; +} + +static int omap3_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; +} static int omap2_clkdm_clk_enable(struct clockdomain *clkdm) { @@ -170,6 +183,17 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm) if (!clkdm->clktrctrl_mask) return 0; + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { + _enable_hwsup(clkdm); + return 0; + } + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); @@ -193,6 +217,17 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm) if (!clkdm->clktrctrl_mask) return 0; + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) && + (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { + omap3_clkdm_wakeup(clkdm); + return 0; + } + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); @@ -209,20 +244,6 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } -static int omap3_clkdm_sleep(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - return 0; -} - -static int omap3_clkdm_wakeup(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - return 0; -} - static void omap3_clkdm_allow_idle(struct clockdomain *clkdm) { if (atomic_read(&clkdm->usecount) > 0) diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index 762f2cc..6fc6155 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) if (!clkdm->prcm_partition) return 0; + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { + omap4_clkdm_allow_idle(clkdm); + return 0; + } + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, clkdm->cm_inst, clkdm->clkdm_offs); diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index 56089c4..933a35c 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c @@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = { .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, }; -/* - * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is - * switched of even if sdti is in use - */ static struct clockdomain emu_clkdm = { .name = "emu_clkdm", .pwrdm = { .name = "emu_pwrdm" }, - .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, + .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP | + CLKDM_MISSING_IDLE_REPORTING), .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, }; diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 63d60a7..b56d06b 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = { .prcm_partition = OMAP4430_PRM_PARTITION, .cm_inst = OMAP4430_PRM_EMU_CM_INST, .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, - .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP, + .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP | + CLKDM_MISSING_IDLE_REPORTING), }; static struct clockdomain l3_dma_44xx_clkdm = { diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index 532027e..adf7bb7 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h @@ -25,263 +25,328 @@ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER */ #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 +#define AM33XX_AUTO_DPLL_MODE_WIDTH 3 #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 +#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 +#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) /* Used by CM_PER_CPSW_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) /* Used by CM_CEFUSE_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) /* Used by CM_L3_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) /* Used by CM_L3_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 +#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) /* Used by CM_GFX_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) /* Used by CM_GFX_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 +#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 +#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 +#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 +#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 +#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 +#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 +#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 +#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) /* Used by CM_PER_PRUSS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) /* Used by CM_PER_PRUSS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) /* Used by CM_PER_PRUSS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) /* Used by CM_PER_L3S_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) /* Used by CM_L3_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) /* Used by CM_PER_L4FW_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) /* Used by CM_PER_L4HS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) /* Used by CM_RTC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 +#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) /* Used by CM_PER_LCDC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) /* Used by CM_PER_LCDC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 +#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) /* Used by CM_PER_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) /* Used by CM_MPU_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) /* Used by CM_RTC_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 +#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 +#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 +#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 +#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 +#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 +#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 +#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 +#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 +#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 +#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) /* Used by CM_PER_L4LS_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 +#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) /* Used by CLKSEL_GFX_FCLK */ #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 +#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) /* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2DIV_SHIFT 3 -#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) +#define AM33XX_CLKOUT2DIV_WIDTH 3 +#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) /* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2EN_SHIFT 7 +#define AM33XX_CLKOUT2EN_WIDTH 1 #define AM33XX_CLKOUT2EN_MASK (1 << 7) /* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2SOURCE_SHIFT 0 -#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) +#define AM33XX_CLKOUT2SOURCE_WIDTH 3 +#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) /* * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, @@ -289,6 +354,7 @@ * CLKSEL_TIMER7_CLK */ #define AM33XX_CLKSEL_SHIFT 0 +#define AM33XX_CLKSEL_WIDTH 1 #define AM33XX_CLKSEL_MASK (0x01 << 0) /* @@ -296,17 +362,21 @@ * CM_CPTS_RFT_CLKSEL */ #define AM33XX_CLKSEL_0_0_SHIFT 0 +#define AM33XX_CLKSEL_0_0_WIDTH 1 #define AM33XX_CLKSEL_0_0_MASK (1 << 0) #define AM33XX_CLKSEL_0_1_SHIFT 0 +#define AM33XX_CLKSEL_0_1_WIDTH 2 #define AM33XX_CLKSEL_0_1_MASK (3 << 0) /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ #define AM33XX_CLKSEL_0_2_SHIFT 0 +#define AM33XX_CLKSEL_0_2_WIDTH 3 #define AM33XX_CLKSEL_0_2_MASK (7 << 0) /* Used by CLKSEL_GFX_FCLK */ #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 +#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) /* @@ -318,6 +388,7 @@ * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL */ #define AM33XX_CLKTRCTRL_SHIFT 0 +#define AM33XX_CLKTRCTRL_WIDTH 2 #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) /* @@ -326,34 +397,42 @@ * CM_SSC_DELTAMSTEP_DPLL_PER */ #define AM33XX_DELTAMSTEP_SHIFT 0 -#define AM33XX_DELTAMSTEP_MASK (0x19 << 0) +#define AM33XX_DELTAMSTEP_WIDTH 20 +#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 +#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) /* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 +#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) /* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 +#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 +#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) +#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 +#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 +#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 +#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) /* @@ -361,6 +440,7 @@ * CM_DIV_M2_DPLL_PER */ #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 +#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) /* @@ -368,19 +448,22 @@ * CM_CLKSEL_DPLL_MPU */ #define AM33XX_DPLL_DIV_SHIFT 0 +#define AM33XX_DPLL_DIV_WIDTH 7 #define AM33XX_DPLL_DIV_MASK (0x7f << 0) #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ #define AM33XX_DPLL_DIV_0_7_SHIFT 0 -#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) +#define AM33XX_DPLL_DIV_0_7_WIDTH 8 +#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) /* * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, * CM_CLKMODE_DPLL_MPU */ #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) /* @@ -388,6 +471,7 @@ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_EN_SHIFT 0 +#define AM33XX_DPLL_EN_WIDTH 3 #define AM33XX_DPLL_EN_MASK (0x7 << 0) /* @@ -395,6 +479,7 @@ * CM_CLKMODE_DPLL_MPU */ #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 +#define AM33XX_DPLL_LPMODE_EN_WIDTH 1 #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) /* @@ -402,10 +487,12 @@ * CM_CLKSEL_DPLL_MPU */ #define AM33XX_DPLL_MULT_SHIFT 8 +#define AM33XX_DPLL_MULT_WIDTH 11 #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 +#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) /* @@ -413,17 +500,20 @@ * CM_CLKMODE_DPLL_MPU */ #define AM33XX_DPLL_REGM4XEN_SHIFT 11 +#define AM33XX_DPLL_REGM4XEN_WIDTH 1 #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) /* Used by CM_CLKSEL_DPLL_PERIPH */ #define AM33XX_DPLL_SD_DIV_SHIFT 24 -#define AM33XX_DPLL_SD_DIV_MASK (24, 31) +#define AM33XX_DPLL_SD_DIV_WIDTH 8 +#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) /* * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_SSC_ACK_SHIFT 13 +#define AM33XX_DPLL_SSC_ACK_WIDTH 1 #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) /* @@ -431,6 +521,7 @@ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) /* @@ -438,54 +529,67 @@ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define AM33XX_DPLL_SSC_EN_SHIFT 12 +#define AM33XX_DPLL_SSC_EN_WIDTH 1 #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) +#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 +#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) /* @@ -522,11 +626,12 @@ * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL */ #define AM33XX_IDLEST_SHIFT 16 +#define AM33XX_IDLEST_WIDTH 2 #define AM33XX_IDLEST_MASK (0x3 << 16) -#define AM33XX_IDLEST_VAL 0x3 /* Used by CM_MAC_CLKSEL */ #define AM33XX_MII_CLK_SEL_SHIFT 2 +#define AM33XX_MII_CLK_SEL_WIDTH 1 #define AM33XX_MII_CLK_SEL_MASK (1 << 2) /* @@ -535,7 +640,8 @@ * CM_SSC_MODFREQDIV_DPLL_PER */ #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) +#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 +#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) /* * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, @@ -543,7 +649,8 @@ * CM_SSC_MODFREQDIV_DPLL_PER */ #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) +#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 +#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) /* * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, @@ -580,42 +687,52 @@ * CM_CEFUSE_CEFUSE_CLKCTRL */ #define AM33XX_MODULEMODE_SHIFT 0 +#define AM33XX_MODULEMODE_WIDTH 2 #define AM33XX_MODULEMODE_MASK (0x3 << 0) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 +#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 +#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) /* Used by CM_WKUP_GPIO0_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO1_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO2_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO3_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO4_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO5_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) /* Used by CM_PER_GPIO6_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) /* @@ -627,25 +744,30 @@ * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL */ #define AM33XX_STBYST_SHIFT 18 +#define AM33XX_STBYST_WIDTH 1 #define AM33XX_STBYST_MASK (1 << 18) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 -#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) +#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 +#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 -#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) +#define AM33XX_STM_PMD_CLKSEL_WIDTH 2 +#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) /* * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER */ #define AM33XX_ST_DPLL_CLK_SHIFT 0 +#define AM33XX_ST_DPLL_CLK_WIDTH 1 #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) /* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 +#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) /* @@ -653,18 +775,22 @@ * CM_DIV_M2_DPLL_PER */ #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 +#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) /* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) /* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) /* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) /* @@ -672,16 +798,20 @@ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER */ #define AM33XX_ST_MN_BYPASS_SHIFT 8 +#define AM33XX_ST_MN_BYPASS_WIDTH 1 #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 -#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) +#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 +#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 -#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) +#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 +#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) /* Used by CONTROL_SEC_CLK_CTRL */ +#define AM33XX_TIMER0_CLKSEL_WIDTH 2 #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 975f6bd..59598ff 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -218,6 +218,8 @@ #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) #define OMAP3430_ST_OMAPCTRL_SHIFT 6 #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) +#define OMAP3430_ST_SAD2D_SHIFT 3 +#define OMAP3430_ST_SAD2D_MASK (1 << 3) #define OMAP3430_ST_SDMA_SHIFT 2 #define OMAP3430_ST_SDMA_MASK (1 << 2) #define OMAP3430_ST_SDRC_SHIFT 1 diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 65597a7..4c6c2f7 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -1,7 +1,7 @@ /* * OMAP44xx Clock Management register bits * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2012 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) @@ -24,6 +24,7 @@ /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_ABE_DYNDEP_SHIFT 3 +#define OMAP4430_ABE_DYNDEP_WIDTH 0x1 #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) /* @@ -31,14 +32,17 @@ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ABE_STATDEP_SHIFT 3 +#define OMAP4430_ABE_STATDEP_WIDTH 0x1 #define OMAP4430_ABE_STATDEP_MASK (1 << 3) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 +#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 +#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) /* @@ -47,294 +51,367 @@ * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB */ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 +#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 +#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 +#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) /* Used by CM_L4CFG_CLKSTCTRL */ #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 +#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) /* Used by CM_DUCATI_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) /* Used by CM_IVAHD_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) /* Used by CM_L3_1_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) /* Used by CM_L3_2_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) /* Used by CM_SDMA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) /* Used by CM_L3INSTR_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) /* Used by CM_L4CFG_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) /* Used by CM_MPU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) /* Used by CM_L4PER_CLKSTCTRL */ @@ -343,94 +420,114 @@ /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) /* Used by CM_L4PER_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) /* Used by CM_MEMIF_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) /* Used by CM_TESLA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) /* Used by CM_L3INIT_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 +#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) /* * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL + * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL */ #define OMAP4430_CLKSEL_SHIFT 24 +#define OMAP4430_CLKSEL_WIDTH 0x1 #define OMAP4430_CLKSEL_MASK (1 << 24) /* @@ -438,50 +535,62 @@ * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 +#define OMAP4430_CLKSEL_0_0_WIDTH 0x1 #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 +#define OMAP4430_CLKSEL_0_1_WIDTH 0x2 #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 +#define OMAP4430_CLKSEL_24_25_WIDTH 0x2 #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 +#define OMAP4430_CLKSEL_60M_WIDTH 0x1 #define OMAP4430_CLKSEL_60M_MASK (1 << 24) /* Used by CM_MPU_MPU_CLKCTRL */ #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) /* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 +#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) /* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 +#define OMAP4430_CLKSEL_CORE_WIDTH 0x1 #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 +#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 +#define OMAP4430_CLKSEL_DIV_WIDTH 0x1 #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) /* Used by CM_MPU_MPU_CLKCTRL */ #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) /* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 +#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) /* @@ -490,34 +599,42 @@ * CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) /* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 +#define OMAP4430_CLKSEL_L3_WIDTH 0x1 #define OMAP4430_CLKSEL_L3_MASK (1 << 4) /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 +#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) /* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 +#define OMAP4430_CLKSEL_L4_WIDTH 0x1 #define OMAP4430_CLKSEL_L4_MASK (1 << 8) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 +#define OMAP4430_CLKSEL_OPP_WIDTH 0x2 #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 +#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) /* Used by CM_GFX_GFX_CLKCTRL */ #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 +#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) /* @@ -525,18 +642,22 @@ * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 +#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 +#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 +#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 +#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) /* @@ -549,30 +670,37 @@ * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKTRCTRL_SHIFT 0 +#define OMAP4430_CLKTRCTRL_WIDTH 0x2 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 +#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 +#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_CUSTOM_SHIFT 6 +#define OMAP4430_CUSTOM_WIDTH 0x2 #define OMAP4430_CUSTOM_MASK (0x3 << 6) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_D2D_DYNDEP_SHIFT 18 +#define OMAP4430_D2D_DYNDEP_WIDTH 0x1 #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) /* Used by CM_MPU_STATICDEP */ #define OMAP4430_D2D_STATDEP_SHIFT 18 +#define OMAP4430_D2D_STATDEP_WIDTH 0x1 #define OMAP4430_D2D_STATDEP_MASK (1 << 18) /* Used by CM_CLKSEL_DPLL_MPU */ #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 +#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) /* Used by CM_CLKSEL_DPLL_MPU */ @@ -586,22 +714,27 @@ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB */ #define OMAP4430_DELTAMSTEP_SHIFT 0 +#define OMAP4430_DELTAMSTEP_WIDTH 0x14 #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 +#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) /* Used by CM_DLL_CTRL */ #define OMAP4430_DLL_OVERRIDE_SHIFT 0 +#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 +#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DLL_RESET_SHIFT 3 +#define OMAP4430_DLL_RESET_WIDTH 0x1 #define OMAP4430_DLL_RESET_MASK (1 << 3) /* @@ -610,30 +743,37 @@ * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 +#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) /* Used by CM_CLKSEL_DPLL_CORE */ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 +#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) /* @@ -641,10 +781,12 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 +#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) /* @@ -652,10 +794,12 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) /* @@ -663,18 +807,22 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 +#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 +#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) /* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 +#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) /* @@ -683,10 +831,12 @@ * CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_DIV_SHIFT 0 +#define OMAP4430_DPLL_DIV_WIDTH 0x7 #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 +#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) /* @@ -694,10 +844,12 @@ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) /* @@ -706,6 +858,7 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_EN_SHIFT 0 +#define OMAP4430_DPLL_EN_WIDTH 0x3 #define OMAP4430_DPLL_EN_MASK (0x7 << 0) /* @@ -714,6 +867,7 @@ * CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 +#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) /* @@ -722,10 +876,12 @@ * CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_MULT_SHIFT 8 +#define OMAP4430_DPLL_MULT_WIDTH 0xb #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_MULT_USB_SHIFT 8 +#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) /* @@ -734,10 +890,12 @@ * CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 +#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) /* Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_SD_DIV_SHIFT 24 +#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) /* @@ -746,6 +904,7 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 +#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) /* @@ -754,6 +913,7 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) /* @@ -762,42 +922,52 @@ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_EN_SHIFT 12 +#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_DSS_DYNDEP_SHIFT 8 +#define OMAP4430_DSS_DYNDEP_WIDTH 0x1 #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DSS_STATDEP_SHIFT 8 +#define OMAP4430_DSS_STATDEP_WIDTH 0x1 #define OMAP4430_DSS_STATDEP_MASK (1 << 8) /* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 +#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 +#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) /* Used by CM_SHADOW_FREQ_CONFIG1 */ #define OMAP4430_FREQ_UPDATE_SHIFT 0 +#define OMAP4430_FREQ_UPDATE_WIDTH 0x1 #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_FUNC_SHIFT 16 +#define OMAP4430_FUNC_WIDTH 0xc #define OMAP4430_FUNC_MASK (0xfff << 16) /* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_GFX_DYNDEP_SHIFT 10 +#define OMAP4430_GFX_DYNDEP_WIDTH 0x1 #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 +#define OMAP4430_GFX_STATDEP_WIDTH 0x1 #define OMAP4430_GFX_STATDEP_MASK (1 << 10) /* Used by CM_SHADOW_FREQ_CONFIG2 */ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 +#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) /* @@ -805,6 +975,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) /* @@ -812,6 +983,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) /* @@ -819,6 +991,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) /* @@ -826,6 +999,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) /* @@ -833,6 +1007,7 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) /* @@ -840,6 +1015,7 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) /* @@ -847,6 +1023,7 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) /* @@ -854,38 +1031,47 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) /* @@ -893,53 +1079,48 @@ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, + * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, + * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, + * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, - * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, - * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, - * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, - * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, - * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, - * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, + * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, + * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, + * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, + * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_IDLEST_SHIFT 16 +#define OMAP4430_IDLEST_WIDTH 0x2 #define OMAP4430_IDLEST_MASK (0x3 << 16) /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ #define OMAP4430_ISS_DYNDEP_SHIFT 9 +#define OMAP4430_ISS_DYNDEP_WIDTH 0x1 #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) /* @@ -947,10 +1128,12 @@ * CM_TESLA_STATICDEP */ #define OMAP4430_ISS_STATDEP_SHIFT 9 +#define OMAP4430_ISS_STATDEP_WIDTH 0x1 #define OMAP4430_ISS_STATDEP_MASK (1 << 9) /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 +#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) /* @@ -959,10 +1142,12 @@ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 +#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 +#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) /* @@ -970,6 +1155,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 +#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) /* @@ -977,6 +1163,7 @@ * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_L3_1_DYNDEP_SHIFT 5 +#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) /* @@ -986,6 +1173,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 +#define OMAP4430_L3_1_STATDEP_WIDTH 0x1 #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) /* @@ -995,6 +1183,7 @@ * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP */ #define OMAP4430_L3_2_DYNDEP_SHIFT 6 +#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) /* @@ -1004,10 +1193,12 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 +#define OMAP4430_L3_2_STATDEP_WIDTH 0x1 #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) /* Used by CM_L3_1_DYNAMICDEP */ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 +#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) /* @@ -1015,10 +1206,12 @@ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 +#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) /* Used by CM_L3_2_DYNAMICDEP */ #define OMAP4430_L4PER_DYNDEP_SHIFT 13 +#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) /* @@ -1026,10 +1219,12 @@ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 +#define OMAP4430_L4PER_STATDEP_WIDTH 0x1 #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 +#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) /* @@ -1037,10 +1232,12 @@ * CM_SDMA_STATICDEP */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 +#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 +#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) /* @@ -1048,6 +1245,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 +#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) /* @@ -1055,6 +1253,7 @@ * CM_MPU_DYNAMICDEP */ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 +#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) /* @@ -1064,6 +1263,7 @@ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 +#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) /* @@ -1073,6 +1273,7 @@ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 +#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) /* @@ -1082,6 +1283,7 @@ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 +#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) /* @@ -1089,69 +1291,68 @@ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, - * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, + * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, + * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, + * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, - * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, - * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, - * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, - * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, + * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, - * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, - * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, - * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, - * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, - * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, - * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, - * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, - * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, + * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, + * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, + * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, - * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, - * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, + * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, + * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_MODULEMODE_SHIFT 0 +#define OMAP4430_MODULEMODE_WIDTH 0x2 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4460_MPU_DYNDEP_SHIFT 19 +#define OMAP4460_MPU_DYNDEP_WIDTH 0x1 #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 +#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) /* Used by CM_ALWON_USBPHY_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) /* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) /* @@ -1160,126 +1361,157 @@ * CM_WKUP_GPIO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 +#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 +#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 +#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 +#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 +#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 +#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 +#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 +#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ #define OMAP4430_PERF_CURRENT_SHIFT 0 +#define OMAP4430_PERF_CURRENT_WIDTH 0x8 #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) /* @@ -1288,74 +1520,85 @@ * CM_IVA_DVFS_PERF_TESLA */ #define OMAP4430_PERF_REQ_SHIFT 0 +#define OMAP4430_PERF_REQ_WIDTH 0x8 #define OMAP4430_PERF_REQ_MASK (0xff << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 +#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 +#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 +#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 +#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 +#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) /* Used by CM_DYN_DEP_PRESCAL */ #define OMAP4430_PRESCAL_SHIFT 0 +#define OMAP4430_PRESCAL_WIDTH 0x6 #define OMAP4430_PRESCAL_MASK (0x3f << 0) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_R_RTL_SHIFT 11 +#define OMAP4430_R_RTL_WIDTH 0x5 #define OMAP4430_R_RTL_MASK (0x1f << 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_SAR_MODE_SHIFT 4 +#define OMAP4430_SAR_MODE_WIDTH 0x1 #define OMAP4430_SAR_MODE_MASK (1 << 4) /* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 +#define OMAP4430_SCALE_FCLK_WIDTH 0x1 #define OMAP4430_SCALE_FCLK_MASK (1 << 0) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_SCHEME_SHIFT 30 +#define OMAP4430_SCHEME_WIDTH 0x2 #define OMAP4430_SCHEME_MASK (0x3 << 30) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_SDMA_DYNDEP_SHIFT 11 +#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_SDMA_STATDEP_SHIFT 11 +#define OMAP4430_SDMA_STATDEP_WIDTH 0x1 #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 +#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) /* * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL */ #define OMAP4430_STBYST_SHIFT 18 +#define OMAP4430_STBYST_WIDTH 0x1 #define OMAP4430_STBYST_MASK (1 << 18) /* @@ -1364,10 +1607,12 @@ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB */ #define OMAP4430_ST_DPLL_CLK_SHIFT 0 +#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 +#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) /* @@ -1375,14 +1620,17 @@ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 +#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 +#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 +#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) /* @@ -1390,6 +1638,7 @@ * CM_DIV_M4_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) /* @@ -1397,14 +1646,17 @@ * CM_DIV_M5_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) /* @@ -1413,18 +1665,22 @@ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB */ #define OMAP4430_ST_MN_BYPASS_SHIFT 8 +#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) /* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 +#define OMAP4430_SYS_CLKSEL_WIDTH 0x3 #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) /* Used by CM_L4CFG_DYNAMICDEP */ #define OMAP4430_TESLA_DYNDEP_SHIFT 1 +#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 +#define OMAP4430_TESLA_STATDEP_WIDTH 0x1 #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) /* @@ -1433,13 +1689,16 @@ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_WINDOWSIZE_SHIFT 24 +#define OMAP4430_WINDOWSIZE_WIDTH 0x4 #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_X_MAJOR_SHIFT 8 +#define OMAP4430_X_MAJOR_WIDTH 0x3 #define OMAP4430_X_MAJOR_MASK (0x7 << 8) /* Used by REVISION_CM1, REVISION_CM2 */ #define OMAP4430_Y_MINOR_SHIFT 0 +#define OMAP4430_Y_MINOR_WIDTH 0x6 #define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index a911e76..7f07ab0 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -35,7 +35,7 @@ #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 static const u8 cm_idlest_offs[] = { - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4 }; u32 omap2_cm_read_mod_reg(s16 module, u16 idx) diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 088bbad..57b2f3c 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -71,6 +71,7 @@ #define OMAP24XX_CM_FCLKEN2 0x0004 #define OMAP24XX_CM_ICLKEN4 0x001c #define OMAP24XX_CM_AUTOIDLE4 0x003c +#define OMAP24XX_CM_IDLEST4 0x002c #define OMAP2430_CM_IDLEST3 0x0028 diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 123186a..a89e825 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -354,6 +354,7 @@ /* AM33XX CONTROL_STATUS bitfields (partial) */ #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 +#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) /* CONTROL OMAP STATUS register to identify OMAP3 features */ diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index d092d2a8..c8c2117 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -433,35 +433,24 @@ static void omap_init_mcspi(void) static inline void omap_init_mcspi(void) {} #endif -static struct resource omap2_pmu_resource = { - .start = 3 + OMAP_INTC_START, - .flags = IORESOURCE_IRQ, -}; - -static struct resource omap3_pmu_resource = { - .start = 3 + OMAP_INTC_START, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device omap_pmu_device = { - .name = "arm-pmu", - .id = -1, - .num_resources = 1, -}; - -static void omap_init_pmu(void) +/** + * omap_init_rng - bind the RNG hwmod to the RNG omap_device + * + * Bind the RNG hwmod to the RNG omap_device. No return value. + */ +static void omap_init_rng(void) { - if (cpu_is_omap24xx()) - omap_pmu_device.resource = &omap2_pmu_resource; - else if (cpu_is_omap34xx()) - omap_pmu_device.resource = &omap3_pmu_resource; - else + struct omap_hwmod *oh; + struct platform_device *pdev; + + oh = omap_hwmod_lookup("rng"); + if (!oh) return; - platform_device_register(&omap_pmu_device); + pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); } - #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) #ifdef CONFIG_ARCH_OMAP2 @@ -646,8 +635,8 @@ static int __init omap2_init_devices(void) omap_init_mcpdm(); omap_init_mcspi(); } - omap_init_pmu(); omap_init_sti(); + omap_init_rng(); omap_init_sham(); omap_init_aes(); omap_init_vout(); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index e470c6e..7012068 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_enable(oc->_clk); + clk_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) - clk_disable(oc->_clk); + clk_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 27d79de..814e180 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const struct dpll_data *dd; int i = 0; int ret = -EINVAL; + const char *clk_name; dd = clk->dpll_data; + clk_name = __clk_get_name(clk); state <<= __ffs(dd->idlest_mask); @@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) if (i == MAX_DPLL_WAIT_TRIES) { printk(KERN_ERR "clock: %s failed transition to '%s'\n", - clk->name, (state) ? "locked" : "bypassed"); + clk_name, (state) ? "locked" : "bypassed"); } else { pr_debug("clock: %s transition to '%s' in %d loops\n", - clk->name, (state) ? "locked" : "bypassed", i); + clk_name, (state) ? "locked" : "bypassed", i); ret = 0; } @@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) unsigned long fint; u16 f = 0; - fint = clk->dpll_data->clk_ref->rate / n; + fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; pr_debug("clock: fint is %lu\n", fint); @@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) u8 state = 1; int r = 0; - pr_debug("clock: locking DPLL %s\n", clk->name); + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", - clk->name); + __clk_get_name(clk)); ai = omap3_dpll_autoidle_read(clk); @@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; - pr_debug("clock: stopping DPLL %s\n", clk->name); + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); ai = omap3_dpll_autoidle_read(clk); @@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) { unsigned long fint, clkinp; /* watch out for overflow */ - clkinp = clk->parent->rate; + clkinp = __clk_get_rate(__clk_get_parent(clk)); fint = (clkinp / n) * m; if (fint < 1000000000) @@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; - clkinp = clk->parent->rate; + clkinp = __clk_get_rate(__clk_get_parent(clk)); /* * target sigma-delta to near 250MHz @@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk) { int r; struct dpll_data *dd; + struct clk *parent; dd = clk->dpll_data; if (!dd) return -EINVAL; - if (clk->rate == dd->clk_bypass->rate) { - WARN_ON(clk->parent != dd->clk_bypass); + parent = __clk_get_parent(clk); + + if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { + WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { - WARN_ON(clk->parent != dd->clk_ref); + WARN_ON(parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); } /* @@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk) int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; - unsigned long hw_rate; + unsigned long hw_rate, bypass_rate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) omap2_clk_enable(dd->clk_bypass); omap2_clk_enable(dd->clk_ref); - if (dd->clk_bypass->rate == rate && + bypass_rate = __clk_get_rate(dd->clk_bypass); + if (bypass_rate == rate && (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); @@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) } pr_debug("clock: %s: set rate: locking rate to %lu.\n", - clk->name, rate); + __clk_get_name(clk), rate); ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, freqsel); @@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk) if (!dd->autoidle_reg) { pr_debug("clock: DPLL %s: autoidle not supported\n", - clk->name); + __clk_get_name(clk)); return; } @@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk) if (!dd->autoidle_reg) { pr_debug("clock: DPLL %s: autoidle not supported\n", - clk->name); + __clk_get_name(clk)); return; } @@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) unsigned long rate; u32 v; struct clk *pclk; + unsigned long parent_rate; /* Walk up the parents of clk, looking for a DPLL */ - pclk = clk->parent; + pclk = __clk_get_parent(clk); while (pclk && !pclk->dpll_data) - pclk = pclk->parent; + pclk = __clk_get_parent(pclk); /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { @@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->enable_mask); + parent_rate = __clk_get_rate(__clk_get_parent(clk)); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) - rate = clk->parent->rate; + rate = parent_rate; else - rate = clk->parent->rate * 2; + rate = parent_rate * 2; return rate; } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 72428bd..8ab1e1b 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -24,6 +24,7 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/interrupt.h> +#include <linux/platform_device.h> #include <asm/mach-types.h> #include <plat/gpmc.h> @@ -31,10 +32,13 @@ #include <plat/cpu.h> #include <plat/gpmc.h> #include <plat/sdrc.h> +#include <plat/omap_device.h> #include "soc.h" #include "common.h" +#define DEVICE_NAME "omap-gpmc" + /* GPMC register offsets */ #define GPMC_REVISION 0x00 #define GPMC_SYSCONFIG 0x10 @@ -83,6 +87,12 @@ #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 +#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) +#define GPMC_REVISION_MINOR(l) (l & 0xf) + +#define GPMC_HAS_WR_ACCESS 0x1 +#define GPMC_HAS_WR_DATA_MUX_BUS 0x2 + /* XXX: Only NAND irq has been considered,currently these are the only ones used */ #define GPMC_NR_IRQ 2 @@ -128,7 +138,10 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ - +static struct device *gpmc_dev; +static int gpmc_irq; +static resource_size_t phys_base, mem_size; +static unsigned gpmc_capability; static void __iomem *gpmc_base; static struct clk *gpmc_l3_clk; @@ -318,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); - if (cpu_is_omap34xx()) { + if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); + if (gpmc_capability & GPMC_HAS_WR_ACCESS) GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); - } /* caller is expected to have initialized CONFIG1 to cover * at least sync vs async @@ -431,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) return r; } +static int gpmc_cs_delete_mem(int cs) +{ + struct resource *res = &gpmc_cs_mem[cs]; + int r; + + spin_lock(&gpmc_mem_lock); + r = release_resource(&gpmc_cs_mem[cs]); + res->start = 0; + res->end = 0; + spin_unlock(&gpmc_mem_lock); + + return r; +} + int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) { struct resource *res = &gpmc_cs_mem[cs]; @@ -767,7 +794,7 @@ static void gpmc_irq_noop(struct irq_data *data) { } static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } -static int gpmc_setup_irq(int gpmc_irq) +static int gpmc_setup_irq(void) { int i; u32 regval; @@ -811,7 +838,37 @@ static int gpmc_setup_irq(int gpmc_irq) return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); } -static void __init gpmc_mem_init(void) +static __exit int gpmc_free_irq(void) +{ + int i; + + if (gpmc_irq) + free_irq(gpmc_irq, NULL); + + for (i = 0; i < GPMC_NR_IRQ; i++) { + irq_set_handler(gpmc_client_irq[i].irq, NULL); + irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); + irq_modify_status(gpmc_client_irq[i].irq, 0, 0); + } + + irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); + + return 0; +} + +static void __devexit gpmc_mem_exit(void) +{ + int cs; + + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + if (!gpmc_cs_mem_enabled(cs)) + continue; + gpmc_cs_delete_mem(cs); + } + +} + +static void __devinit gpmc_mem_init(void) { int cs; unsigned long boot_rom_space = 0; @@ -838,65 +895,104 @@ static void __init gpmc_mem_init(void) } } -static int __init gpmc_init(void) +static __devinit int gpmc_probe(struct platform_device *pdev) { u32 l; - int ret = -EINVAL; - int gpmc_irq; - char *ck = NULL; - - if (cpu_is_omap24xx()) { - ck = "core_l3_ck"; - if (cpu_is_omap2420()) - l = OMAP2420_GPMC_BASE; - else - l = OMAP34XX_GPMC_BASE; - gpmc_irq = 20 + OMAP_INTC_START; - } else if (cpu_is_omap34xx()) { - ck = "gpmc_fck"; - l = OMAP34XX_GPMC_BASE; - gpmc_irq = 20 + OMAP_INTC_START; - } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { - /* Base address and irq number are same for OMAP4/5 */ - ck = "gpmc_ck"; - l = OMAP44XX_GPMC_BASE; - gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENOENT; + + phys_base = res->start; + mem_size = resource_size(res); + + gpmc_base = devm_request_and_ioremap(&pdev->dev, res); + if (!gpmc_base) { + dev_err(&pdev->dev, "error: request memory / ioremap\n"); + return -EADDRNOTAVAIL; } - if (WARN_ON(!ck)) - return ret; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) + dev_warn(&pdev->dev, "Failed to get resource: irq\n"); + else + gpmc_irq = res->start; - gpmc_l3_clk = clk_get(NULL, ck); + gpmc_l3_clk = clk_get(&pdev->dev, "fck"); if (IS_ERR(gpmc_l3_clk)) { - printk(KERN_ERR "Could not get GPMC clock %s\n", ck); - BUG(); + dev_err(&pdev->dev, "error: clk_get\n"); + gpmc_irq = 0; + return PTR_ERR(gpmc_l3_clk); } - gpmc_base = ioremap(l, SZ_4K); - if (!gpmc_base) { - clk_put(gpmc_l3_clk); - printk(KERN_ERR "Could not get GPMC register memory\n"); - BUG(); - } + clk_prepare_enable(gpmc_l3_clk); - clk_enable(gpmc_l3_clk); + gpmc_dev = &pdev->dev; l = gpmc_read_reg(GPMC_REVISION); - printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - /* Set smart idle mode and automatic L3 clock gating */ - l = gpmc_read_reg(GPMC_SYSCONFIG); - l &= 0x03 << 3; - l |= (0x02 << 3) | (1 << 0); - gpmc_write_reg(GPMC_SYSCONFIG, l); + if (GPMC_REVISION_MAJOR(l) > 0x4) + gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; + dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), + GPMC_REVISION_MINOR(l)); + gpmc_mem_init(); - ret = gpmc_setup_irq(gpmc_irq); - if (ret) - pr_err("gpmc: irq-%d could not claim: err %d\n", - gpmc_irq, ret); - return ret; + if (IS_ERR_VALUE(gpmc_setup_irq())) + dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); + + return 0; } + +static __exit int gpmc_remove(struct platform_device *pdev) +{ + gpmc_free_irq(); + gpmc_mem_exit(); + gpmc_dev = NULL; + return 0; +} + +static struct platform_driver gpmc_driver = { + .probe = gpmc_probe, + .remove = __devexit_p(gpmc_remove), + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + }, +}; + +static __init int gpmc_init(void) +{ + return platform_driver_register(&gpmc_driver); +} + +static __exit void gpmc_exit(void) +{ + platform_driver_unregister(&gpmc_driver); + +} + postcore_initcall(gpmc_init); +module_exit(gpmc_exit); + +static int __init omap_gpmc_init(void) +{ + struct omap_hwmod *oh; + struct platform_device *pdev; + char *oh_name = "gpmc"; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -ENODEV; + } + + pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); + + return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; +} +postcore_initcall(omap_gpmc_init); static irqreturn_t gpmc_handle_irq(int irq, void *dev) { diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 00c0066..299ca28 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh) if (!oh->main_clk) return 0; - oh->_clk = omap_clk_get_by_name(oh->main_clk); - if (!oh->_clk) { + oh->_clk = clk_get(NULL, oh->main_clk); + if (IS_ERR(oh->_clk)) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); return -EINVAL; } + /* + * HACK: This needs a re-visit once clk_prepare() is implemented + * to do something meaningful. Today its just a no-op. + * If clk_prepare() is used at some point to do things like + * voltage scaling etc, then this would have to be moved to + * some point where subsystems like i2c and pmic become + * available. + */ + clk_prepare(oh->_clk); if (!oh->_clk->clkdm) - pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", - oh->main_clk, oh->_clk->name); + pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", + oh->name, oh->main_clk); return ret; } @@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh) if (!os->clk) continue; - c = omap_clk_get_by_name(os->clk); - if (!c) { + c = clk_get(NULL, os->clk); + if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); ret = -EINVAL; } os->_clk = c; + /* + * HACK: This needs a re-visit once clk_prepare() is implemented + * to do something meaningful. Today its just a no-op. + * If clk_prepare() is used at some point to do things like + * voltage scaling etc, then this would have to be moved to + * some point where subsystems like i2c and pmic become + * available. + */ + clk_prepare(os->_clk); } return ret; @@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh) int ret = 0; for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { - c = omap_clk_get_by_name(oc->clk); - if (!c) { + c = clk_get(NULL, oc->clk); + if (IS_ERR(c)) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); ret = -EINVAL; } oc->_clk = c; + /* + * HACK: This needs a re-visit once clk_prepare() is implemented + * to do something meaningful. Today its just a no-op. + * If clk_prepare() is used at some point to do things like + * voltage scaling etc, then this would have to be moved to + * some point where subsystems like i2c and pmic become + * available. + */ + clk_prepare(oc->_clk); } return ret; @@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) { pr_debug("omap_hwmod: enable %s:%s\n", oc->role, - oc->_clk->name); + __clk_get_name(oc->_clk)); clk_enable(oc->_clk); } } @@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) if (oc->_clk) { pr_debug("omap_hwmod: disable %s:%s\n", oc->role, - oc->_clk->name); + __clk_get_name(oc->_clk)); clk_disable(oc->_clk); } } @@ -900,10 +927,10 @@ static void _am33xx_enable_module(struct omap_hwmod *oh) */ static int _omap4_wait_target_disable(struct omap_hwmod *oh) { - if (!oh || !oh->clkdm) + if (!oh) return -EINVAL; - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) return 0; if (oh->flags & HWMOD_NO_IDLEST) @@ -1427,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name) */ static int _init_clkdm(struct omap_hwmod *oh) { - if (!oh->clkdm_name) + if (!oh->clkdm_name) { + pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); return 0; + } oh->clkdm = clkdm_lookup(oh->clkdm_name); if (!oh->clkdm) { @@ -1556,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) { struct omap_hwmod_rst_info ohri; int ret = -EINVAL; + int hwsup = 0; if (!oh) return -EINVAL; @@ -1567,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) if (IS_ERR_VALUE(ret)) return ret; + if (oh->clkdm) { + /* + * A clockdomain must be in SW_SUP otherwise reset + * might not be completed. The clockdomain can be set + * in HW_AUTO only when the module become ready. + */ + hwsup = clkdm_in_hwsup(oh->clkdm); + ret = clkdm_hwmod_enable(oh->clkdm, oh); + if (ret) { + WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", + oh->name, oh->clkdm->name, ret); + return ret; + } + } + + _enable_clocks(oh); + if (soc_ops.enable_module) + soc_ops.enable_module(oh); + ret = soc_ops.deassert_hardreset(oh, &ohri); + + if (soc_ops.disable_module) + soc_ops.disable_module(oh); + _disable_clocks(oh); + if (ret == -EBUSY) pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); + if (!ret) { + /* + * Set the clockdomain to HW_AUTO, assuming that the + * previous state was HW_AUTO. + */ + if (oh->clkdm && hwsup) + clkdm_allow_idle(oh->clkdm); + } else { + if (oh->clkdm) + clkdm_hwmod_disable(oh->clkdm, oh); + } + return ret; } @@ -1605,25 +1671,28 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) } /** - * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset + * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset * @oh: struct omap_hwmod * * - * If any hardreset line associated with @oh is asserted, then return true. - * Otherwise, if @oh has no hardreset lines associated with it, or if - * no hardreset lines associated with @oh are asserted, then return false. + * If all hardreset lines associated with @oh are asserted, then return true. + * Otherwise, if part of @oh is out hardreset or if no hardreset lines + * associated with @oh are asserted, then return false. * This function is used to avoid executing some parts of the IP block - * enable/disable sequence if a hardreset line is set. + * enable/disable sequence if its hardreset line is set. */ -static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) +static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) { - int i; + int i, rst_cnt = 0; if (oh->rst_lines_cnt == 0) return false; for (i = 0; i < oh->rst_lines_cnt; i++) if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) - return true; + rst_cnt++; + + if (oh->rst_lines_cnt == rst_cnt) + return true; return false; } @@ -1642,6 +1711,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh) if (!oh->clkdm || !oh->prcm.omap4.modulemode) return -EINVAL; + /* + * Since integration code might still be doing something, only + * disable if all lines are under hardreset. + */ + if (!_are_all_hardreset_lines_asserted(oh)) + return 0; + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); omap4_cminst_module_disable(oh->clkdm->prcm_partition, @@ -1649,9 +1725,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh) oh->clkdm->clkdm_offs, oh->prcm.omap4.clkctrl_offs); - if (_are_any_hardreset_lines_asserted(oh)) - return 0; - v = _omap4_wait_target_disable(oh); if (v) pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", @@ -1679,7 +1752,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh) am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, oh->prcm.omap4.clkctrl_offs); - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; v = _am33xx_wait_target_disable(oh); @@ -1907,7 +1980,7 @@ static int _enable(struct omap_hwmod *oh) } /* - * If an IP block contains HW reset lines and any of them are + * If an IP block contains HW reset lines and all of them are * asserted, we let integration code associated with that * block handle the enable. We've received very little * information on what those driver authors need, and until @@ -1915,7 +1988,7 @@ static int _enable(struct omap_hwmod *oh) * posted to the public lists, this is probably the best we * can do. */ - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; /* Mux pins for device runtime if populated */ @@ -1934,7 +2007,8 @@ static int _enable(struct omap_hwmod *oh) * completely the module. The clockdomain can be set * in HW_AUTO only when the module become ready. */ - hwsup = clkdm_in_hwsup(oh->clkdm); + hwsup = clkdm_in_hwsup(oh->clkdm) && + !clkdm_missing_idle_reporting(oh->clkdm); r = clkdm_hwmod_enable(oh->clkdm, oh); if (r) { WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", @@ -1996,7 +2070,7 @@ static int _idle(struct omap_hwmod *oh) return -EINVAL; } - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; if (oh->class->sysc) @@ -2084,7 +2158,7 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } - if (_are_any_hardreset_lines_asserted(oh)) + if (_are_all_hardreset_lines_asserted(oh)) return 0; pr_debug("omap_hwmod: %s: disabling\n", oh->name); @@ -2608,10 +2682,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh) */ static int _omap4_wait_target_ready(struct omap_hwmod *oh) { - if (!oh || !oh->clkdm) + if (!oh) return -EINVAL; - if (oh->flags & HWMOD_NO_IDLEST) + if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) return 0; if (!_find_mpu_rt_port(oh)) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 10575a1..b5db600 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -536,6 +536,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = { + { + .pa_start = 0x6800a000, + .pa_end = 0x6800afff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, @@ -544,6 +553,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_gpmc_hwmod, + .clk = "core_l3_ck", + .addr = omap2420_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -585,8 +602,10 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, &omap2420_l4_core__msdi1, + &omap2xxx_l4_core__rng, &omap2420_l4_core__hdq1w, &omap2420_l4_wkup__counter_32k, + &omap2420_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 60de70f..c455e41 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -888,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = { + { + .pa_start = 0x6e000000, + .pa_end = 0x6e000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { .master = &omap2xxx_l4_wkup_hwmod, .slave = &omap2xxx_counter_32k_hwmod, @@ -896,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_gpmc_hwmod, + .clk = "core_l3_ck", + .addr = omap2430_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l3_main__l4_core, &omap2xxx_mpu__l3_main, @@ -945,7 +962,9 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l4_core__mcbsp4, &omap2430_l4_core__mcbsp5, &omap2430_l4_core__hdq1w, + &omap2xxx_l4_core__rng, &omap2430_l4_wkup__counter_32k, + &omap2430_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index f853a0b..1a1287d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap2_rng_addr_space[] = { + { + .pa_start = 0x480a0000, + .pa_end = 0x480a004f, + .flags = ADDR_TYPE_RT + }, + { } +}; + /* * Common interconnect data */ @@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> rng */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_rng_hwmod, + .clk = "rng_ick", + .addr = omap2_rng_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index feeb401..35dcdb6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -173,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = { }; /* + * 'gpmc' class + * general purpose memory controller + */ + +static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &omap2xxx_gpmc_sysc, +}; + +/* * IP blocks */ @@ -198,8 +218,14 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = { }; /* MPU */ +static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = { + { .name = "pmu", .irq = 3 }, + { .irq = -1 } +}; + struct omap_hwmod omap2xxx_mpu_hwmod = { .name = "mpu", + .mpu_irqs = omap2xxx_mpu_irqs, .class = &mpu_hwmod_class, .main_clk = "mpu_ck", }; @@ -220,6 +246,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { .timer_capability = OMAP_TIMER_HAS_PWM, }; +/* timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, +}; + /* timer1 */ struct omap_hwmod omap2xxx_timer1_hwmod = { @@ -308,6 +339,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -326,6 +358,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -344,6 +377,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -362,6 +396,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -724,7 +759,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { .dev_attr = &omap_mcspi2_dev_attr, }; - static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { .name = "counter", }; @@ -743,3 +777,77 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = { }, .class = &omap2xxx_counter_hwmod_class, }; + +/* gpmc */ +static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = { + { .irq = 20 }, + { .irq = -1 } +}; + +struct omap_hwmod omap2xxx_gpmc_hwmod = { + .name = "gpmc", + .class = &omap2xxx_gpmc_hwmod_class, + .mpu_irqs = omap2xxx_gpmc_irqs, + .main_clk = "gpmc_fck", + /* + * XXX HWMOD_INIT_NO_RESET should not be needed for this IP + * block. It is not being added due to any known bugs with + * resetting the GPMC IP block, but rather because any timings + * set by the bootloader are not being correctly programmed by + * the kernel from the board file or DT data. + * HWMOD_INIT_NO_RESET should be removed ASAP. + */ + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | + HWMOD_NO_IDLEST), + .prcm = { + .omap2 = { + .prcm_reg_id = 3, + .module_bit = OMAP24XX_EN_GPMC_MASK, + .module_offs = CORE_MOD, + }, + }, +}; + +/* RNG */ + +static struct omap_hwmod_class_sysconfig omap2_rng_sysc = { + .rev_offs = 0x3c, + .sysc_offs = 0x40, + .syss_offs = 0x44, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2_rng_hwmod_class = { + .name = "rng", + .sysc = &omap2_rng_sysc, +}; + +static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = { + { .irq = 52 }, + { .irq = -1 } +}; + +struct omap_hwmod omap2xxx_rng_hwmod = { + .name = "rng", + .mpu_irqs = omap2_rng_mpu_irqs, + .main_clk = "l4_ck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 4, + .module_bit = OMAP24XX_EN_RNG_SHIFT, + .idlest_reg_id = 4, + .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT, + }, + }, + /* + * XXX The first read from the SYSSTATUS register of the RNG + * after the SYSCONFIG SOFTRESET bit is set triggers an + * imprecise external abort. It's unclear why this happens. + * Until this is analyzed, skip the IP block reset. + */ + .flags = HWMOD_INIT_NO_RESET, + .class = &omap2_rng_hwmod_class, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 94b38af..2857772 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -27,6 +27,7 @@ #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <plat/dmtimer.h> +#include <plat/iommu.h> #include "am35xx.h" @@ -92,8 +93,14 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = { }; /* MPU */ +static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { + { .name = "pmu", .irq = 3 }, + { .irq = -1 } +}; + static struct omap_hwmod omap3xxx_mpu_hwmod = { .name = "mpu", + .mpu_irqs = omap3xxx_mpu_irqs, .class = &mpu_hwmod_class, .main_clk = "arm_fck", }; @@ -123,6 +130,24 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { }, }; +/* + * 'debugss' class + * debug and emulation sub system + */ + +static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { + .name = "debugss", +}; + +/* debugss */ +static struct omap_hwmod omap3xxx_debugss_hwmod = { + .name = "debugss", + .class = &omap3xxx_debugss_hwmod_class, + .clkdm_name = "emu_clkdm", + .main_clk = "emu_src_ck", + .flags = HWMOD_NO_IDLEST, +}; + /* timer class */ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { .rev_offs = 0x0000, @@ -170,6 +195,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { .timer_capability = OMAP_TIMER_HAS_PWM, }; +/* timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, +}; + +/* pwm timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, +}; + /* timer1 */ static struct omap_hwmod omap3xxx_timer1_hwmod = { .name = "timer1", @@ -253,6 +288,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -270,6 +306,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -287,6 +324,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, }, }, + .dev_attr = &capability_dsp_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -304,7 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, + .dev_attr = &capability_dsp_pwm_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -2033,6 +2071,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = { .class = &omap2_hdq1w_class, }; +/* SAD2D */ +static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { + { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, + { .name = "rst_modem_sw", .rst_shift = 1 }, +}; + +static struct omap_hwmod_class omap3xxx_sad2d_class = { + .name = "sad2d", +}; + +static struct omap_hwmod omap3xxx_sad2d_hwmod = { + .name = "sad2d", + .rst_lines = omap3xxx_sad2d_resets, + .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), + .main_clk = "sad2d_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SAD2D_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, + }, + }, + .class = &omap3xxx_sad2d_class, +}; + /* * '32K sync counter' class * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock @@ -2068,6 +2133,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = { }; /* + * 'gpmc' class + * general purpose memory controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &omap3xxx_gpmc_sysc, +}; + +static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { + { .irq = 20 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap3xxx_gpmc_hwmod = { + .name = "gpmc", + .class = &omap3xxx_gpmc_hwmod_class, + .clkdm_name = "core_l3_clkdm", + .mpu_irqs = omap3xxx_gpmc_irqs, + .main_clk = "gpmc_fck", + /* + * XXX HWMOD_INIT_NO_RESET should not be needed for this IP + * block. It is not being added due to any known bugs with + * resetting the GPMC IP block, but rather because any timings + * set by the bootloader are not being correctly programmed by + * the kernel from the board file or DT data. + * HWMOD_INIT_NO_RESET should be removed ASAP. + */ + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | + HWMOD_NO_IDLEST), +}; + +/* * interfaces */ @@ -2102,6 +2210,23 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { + { + .pa_start = 0x54000000, + .pa_end = 0x547fffff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3 -> debugss */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_debugss_hwmod, + .addr = omap3xxx_l4_emu_addrs, + .user = OCP_USER_MPU, +}; + /* DSS -> l3 */ static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { .master = &omap3430es1_dss_core_hwmod, @@ -2137,6 +2262,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { .user = OCP_USER_MPU, }; +/* l3_core -> sad2d interface */ +static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { + .master = &omap3xxx_sad2d_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .master = &omap3xxx_l4_core_hwmod, @@ -2823,6 +2956,122 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig mmu_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &mmu_sysc, +}; + +/* mmu isp */ + +static struct omap_mmu_dev_attr mmu_isp_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 8, +}; + +static struct omap_hwmod omap3xxx_mmu_isp_hwmod; +static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { + { .irq = 24 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { + { + .pa_start = 0x480bd400, + .pa_end = 0x480bd47f, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> mmu isp */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmu_isp_hwmod, + .addr = omap3xxx_mmu_isp_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { + .name = "mmu_isp", + .class = &omap3xxx_mmu_hwmod_class, + .mpu_irqs = omap3xxx_mmu_isp_irqs, + .main_clk = "cam_ick", + .dev_attr = &mmu_isp_dev_attr, + .flags = HWMOD_NO_IDLEST, +}; + +#ifdef CONFIG_OMAP_IOMMU_IVA2 + +/* mmu iva */ + +static struct omap_mmu_dev_attr mmu_iva_dev_attr = { + .da_start = 0x11000000, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap3xxx_mmu_iva_hwmod; +static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { + { .irq = 28 }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { + { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { + { + .pa_start = 0x5d000000, + .pa_end = 0x5d00007f, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3_main -> iva mmu */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_mmu_iva_hwmod, + .addr = omap3xxx_mmu_iva_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { + .name = "mmu_iva", + .class = &omap3xxx_mmu_hwmod_class, + .mpu_irqs = omap3xxx_mmu_iva_irqs, + .rst_lines = omap3xxx_mmu_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), + .main_clk = "iva2_ck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_IVA2_MOD, + }, + }, + .dev_attr = &mmu_iva_dev_attr, + .flags = HWMOD_NO_IDLEST, +}; + +#endif + /* l4_per -> gpio4 */ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { { @@ -3168,6 +3417,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { { } }; +static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { + { + .pa_start = 0x6e000000, + .pa_end = 0x6e000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { .master = &omap3xxx_l4_wkup_hwmod, .slave = &omap3xxx_counter_32k_hwmod, @@ -3277,10 +3535,19 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_gpmc_hwmod, + .clk = "core_l3_ick", + .addr = omap3xxx_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, &omap3xxx_mpu__l3_main, + &omap3xxx_l3_main__l4_debugss, &omap3xxx_l4_core__l4_wkup, &omap3xxx_l4_core__mmc3, &omap3_l4_core__uart1, @@ -3322,6 +3589,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__mcspi3, &omap34xx_l4_core__mcspi4, &omap3xxx_l4_wkup__counter_32k, + &omap3xxx_l3_main__gpmc, NULL, }; @@ -3371,6 +3639,11 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__sr2, &omap3xxx_l4_core__mailbox, &omap3xxx_l4_core__hdq1w, + &omap3xxx_sad2d__l3, + &omap3xxx_l4_core__mmu_isp, +#ifdef CONFIG_OMAP_IOMMU_IVA2 + &omap3xxx_l3_main__mmu_iva, +#endif NULL }; @@ -3391,6 +3664,11 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc2, &omap3xxx_l4_core__hdq1w, + &omap3xxx_sad2d__l3, + &omap3xxx_l4_core__mmu_isp, +#ifdef CONFIG_OMAP_IOMMU_IVA2 + &omap3xxx_l3_main__mmu_iva, +#endif NULL }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c7dcb60..8d7a935 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -30,6 +30,7 @@ #include <plat/mmc.h> #include <plat/dmtimer.h> #include <plat/common.h> +#include <plat/iommu.h> #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" @@ -202,6 +203,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, + .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, }, }, }; @@ -258,6 +262,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { .name = "mpu_private", .class = &omap44xx_mpu_bus_hwmod_class, .clkdm_name = "mpuss_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* @@ -342,6 +351,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, + .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -446,6 +456,11 @@ static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_cfg_clkdm", .mpu_irqs = omap44xx_ctrl_module_core_irqs, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* ctrl_module_pad_core */ @@ -453,6 +468,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { .name = "ctrl_module_pad_core", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_cfg_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* ctrl_module_wkup */ @@ -460,6 +480,11 @@ static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { .name = "ctrl_module_wkup", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* ctrl_module_pad_wkup */ @@ -467,6 +492,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { .name = "ctrl_module_pad_wkup", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* @@ -611,7 +641,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { { .name = "dsp", .rst_shift = 0 }, - { .name = "mmu_cache", .rst_shift = 1 }, }; static struct omap_hwmod omap44xx_dsp_hwmod = { @@ -1323,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { .name = "gpmc", .class = &omap44xx_gpmc_hwmod_class, .clkdm_name = "l3_2_clkdm", + /* + * XXX HWMOD_INIT_NO_RESET should not be needed for this IP + * block. It is not being added due to any known bugs with + * resetting the GPMC IP block, but rather because any timings + * set by the bootloader are not being correctly programmed by + * the kernel from the board file or DT data. + * HWMOD_INIT_NO_RESET should be removed ASAP. + */ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_gpmc_irqs, .sdma_reqs = omap44xx_gpmc_sdma_reqs, @@ -1631,7 +1668,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "cpu0", .rst_shift = 0 }, { .name = "cpu1", .rst_shift = 1 }, - { .name = "mmu_cache", .rst_shift = 2 }, }; static struct omap_hwmod omap44xx_ipu_hwmod = { @@ -2438,6 +2474,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig mmu_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &mmu_sysc, +}; + +/* mmu ipu */ + +static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap44xx_mmu_ipu_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { + { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { + { + .pa_start = 0x55082000, + .pa_end = 0x550820ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l3_main_2 -> mmu_ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_mmu_ipu_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_mmu_ipu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { + .name = "mmu_ipu", + .class = &omap44xx_mmu_hwmod_class, + .clkdm_name = "ducati_clkdm", + .mpu_irqs = omap44xx_mmu_ipu_irqs, + .rst_lines = omap44xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), + .main_clk = "ducati_clk_mux_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, + .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .dev_attr = &mmu_ipu_dev_attr, +}; + +/* mmu dsp */ + +static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { + .da_start = 0x0, + .da_end = 0xfffff000, + .nr_tlb_entries = 32, +}; + +static struct omap_hwmod omap44xx_mmu_dsp_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { + { .irq = 28 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { + { + .pa_start = 0x4a066000, + .pa_end = 0x4a0660ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mmu_dsp_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmu_dsp_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { + .name = "mmu_dsp", + .class = &omap44xx_mmu_hwmod_class, + .clkdm_name = "tesla_clkdm", + .mpu_irqs = omap44xx_mmu_dsp_irqs, + .rst_lines = omap44xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), + .main_clk = "dpll_iva_m4x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, + .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .dev_attr = &mmu_dsp_dev_attr, +}; + +/* * 'mpu' class * mpu sub-system */ @@ -2448,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { /* mpu */ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { + { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START }, + { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START }, { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, @@ -2497,19 +2666,27 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { * protocol */ +static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { .name = "ocp2scp", + .sysc = &omap44xx_ocp2scp_sysc, }; /* ocp2scp_usb_phy */ -static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { - { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, -}; - static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", .class = &omap44xx_ocp2scp_hwmod_class, .clkdm_name = "l3_init_clkdm", + .main_clk = "ocp2scp_usb_phy_phy_48m", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, @@ -2517,8 +2694,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .opt_clks = ocp2scp_usb_phy_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), }; /* @@ -2536,18 +2711,36 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { .name = "prcm_mpu", .class = &omap44xx_prcm_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* cm_core_aon */ static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { .name = "cm_core_aon", .class = &omap44xx_prcm_hwmod_class, + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* cm_core */ static struct omap_hwmod omap44xx_cm_core_hwmod = { .name = "cm_core", .class = &omap44xx_prcm_hwmod_class, + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* prm */ @@ -2583,6 +2776,11 @@ static struct omap_hwmod omap44xx_scrm_hwmod = { .name = "scrm", .class = &omap44xx_scrm_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, }; /* @@ -2901,6 +3099,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { .timer_capability = OMAP_TIMER_HAS_PWM, }; +/* timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, +}; + +/* pwm timers with DSP interrupt dev attribute */ +static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, +}; + /* timer1 */ static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { { .irq = 37 + OMAP44XX_IRQ_GIC_START }, @@ -3005,6 +3213,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_dsp_dev_attr, }; /* timer6 */ @@ -3027,6 +3236,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_dsp_dev_attr, }; /* timer7 */ @@ -3048,6 +3258,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, + .dev_attr = &capability_dsp_dev_attr, }; /* timer8 */ @@ -3069,7 +3280,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_pwm_dev_attr, + .dev_attr = &capability_dsp_pwm_dev_attr, }; /* timer9 */ @@ -5262,11 +5473,21 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { + { + .pa_start = 0x4a0ad000, + .pa_end = 0x4a0ad01f, + .flags = ADDR_TYPE_RT + }, + { } +}; + /* l4_cfg -> ocp2scp_usb_phy */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_ocp2scp_usb_phy_hwmod, .clk = "l4_div_ck", + .addr = omap44xx_ocp2scp_usb_phy_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5886,7 +6107,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { { .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab003, + .pa_end = 0x4a0ab7ff, .flags = ADDR_TYPE_RT }, { @@ -6097,6 +6318,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__mmc3, &omap44xx_l4_per__mmc4, &omap44xx_l4_per__mmc5, + &omap44xx_l3_main_2__mmu_ipu, + &omap44xx_l4_cfg__mmu_dsp, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_l4_cfg__ocp2scp_usb_phy, &omap44xx_mpu_private__prcm_mpu, diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index dddb677..2bc8f17 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -2,9 +2,8 @@ * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations * * Copyright (C) 2010-2011 Nokia Corporation + * Copyright (C) 2010-2012 Texas Instruments, Inc. * Paul Walmsley - * - * Copyright (C) 2010-2011 Texas Instruments, Inc. * Benoît Cousson * * This program is free software; you can redistribute it and/or modify @@ -77,6 +76,8 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod; extern struct omap_hwmod omap2xxx_mcspi1_hwmod; extern struct omap_hwmod omap2xxx_mcspi2_hwmod; extern struct omap_hwmod omap2xxx_counter_32k_hwmod; +extern struct omap_hwmod omap2xxx_gpmc_hwmod; +extern struct omap_hwmod omap2xxx_rng_hwmod; /* Common interface data across OMAP2xxx */ extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; @@ -103,6 +104,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; /* Common IP block data */ extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 939bd6f..abefbc4 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -80,7 +80,8 @@ static void __init omap2_init_processor_devices(void) int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) { - if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) + if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && + !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && atomic_read(&clkdm->usecount) == 0) @@ -188,7 +189,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, goto exit; } - freq = clk->rate; + freq = clk_get_rate(clk); clk_put(clk); rcu_read_lock(); diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c new file mode 100644 index 0000000..2a79176 --- /dev/null +++ b/arch/arm/mach-omap2/pmu.c @@ -0,0 +1,95 @@ +/* + * OMAP2 ARM Performance Monitoring Unit (PMU) Support + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * Contacts: + * Jon Hunter <jon-hunter@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/pm_runtime.h> + +#include <asm/pmu.h> + +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> + +static char *omap2_pmu_oh_names[] = {"mpu"}; +static char *omap3_pmu_oh_names[] = {"mpu", "debugss"}; +static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"}; +static struct platform_device *omap_pmu_dev; + +/** + * omap2_init_pmu - creates and registers PMU platform device + * @oh_num: Number of OMAP HWMODs required to create PMU device + * @oh_names: Array of OMAP HWMODS names required to create PMU device + * + * Uses OMAP HWMOD framework to create and register an ARM PMU device + * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3 + * and OMAP4 devices. + */ +static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[]) +{ + int i; + struct omap_hwmod *oh[3]; + char *dev_name = "arm-pmu"; + + if ((!oh_num) || (oh_num > 3)) + return -EINVAL; + + for (i = 0; i < oh_num; i++) { + oh[i] = omap_hwmod_lookup(oh_names[i]); + if (!oh[i]) { + pr_err("Could not look up %s hwmod\n", oh_names[i]); + return -ENODEV; + } + } + + omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0, + NULL, 0, 0); + WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", + dev_name); + + if (IS_ERR(omap_pmu_dev)) + return PTR_ERR(omap_pmu_dev); + + pm_runtime_enable(&omap_pmu_dev->dev); + + return 0; +} + +static int __init omap_init_pmu(void) +{ + unsigned oh_num; + char **oh_names; + + /* + * To create an ARM-PMU device the following HWMODs + * are required for the various OMAP2+ devices. + * + * OMAP24xx: mpu + * OMAP3xxx: mpu, debugss + * OMAP4430: l3_main_3, l3_instr, debugss + * OMAP4460/70: mpu, debugss + */ + if (cpu_is_omap443x()) { + oh_num = ARRAY_SIZE(omap4430_pmu_oh_names); + oh_names = omap4430_pmu_oh_names; + /* XXX Remove the next two lines when CTI driver available */ + pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n"); + return 0; + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + oh_num = ARRAY_SIZE(omap3_pmu_oh_names); + oh_names = omap3_pmu_oh_names; + } else { + oh_num = ARRAY_SIZE(omap2_pmu_oh_names); + oh_names = omap2_pmu_oh_names; + } + + return omap2_init_pmu(oh_num, oh_names); +} +subsys_initcall(omap_init_pmu); diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index aeac6f3..aceb4f4 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -1,7 +1,7 @@ /* * OMAP4 powerdomain control * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation * * Derived from mach-omap2/powerdomain.c written by Paul Walmsley @@ -151,6 +151,34 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) return v; } +/** + * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate + * @pwrdm: struct powerdomain * to read the state for + * + * Reads the previous logic powerstate for a powerdomain. This + * function must determine the previous logic powerstate by first + * checking the previous powerstate for the domain. If that was OFF, + * then logic has been lost. If previous state was RETENTION, the + * function reads the setting for the next retention logic state to + * see the actual value. In every other case, the logic is + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET + * depending whether the logic was retained or not. + */ +static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) +{ + int state; + + state = omap4_pwrdm_read_prev_pwrst(pwrdm); + + if (state == PWRDM_POWER_OFF) + return PWRDM_POWER_OFF; + + if (state != PWRDM_POWER_RET) + return PWRDM_POWER_RET; + + return omap4_pwrdm_read_logic_retst(pwrdm); +} + static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) { u32 m, v; @@ -179,6 +207,35 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) return v; } +/** + * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate + * @pwrdm: struct powerdomain * to read mem powerstate for + * @bank: memory bank index + * + * Reads the previous memory powerstate for a powerdomain. This + * function must determine the previous memory powerstate by first + * checking the previous powerstate for the domain. If that was OFF, + * then logic has been lost. If previous state was RETENTION, the + * function reads the setting for the next memory retention state to + * see the actual value. In every other case, the logic is + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET + * depending whether logic was retained or not. + */ +static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + int state; + + state = omap4_pwrdm_read_prev_pwrst(pwrdm); + + if (state == PWRDM_POWER_OFF) + return PWRDM_POWER_OFF; + + if (state != PWRDM_POWER_RET) + return PWRDM_POWER_RET; + + return omap4_pwrdm_read_mem_retst(pwrdm, bank); +} + static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) { u32 c = 0; @@ -217,9 +274,11 @@ struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, + .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst, .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, + .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst, .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, .pwrdm_wait_transition = omap4_pwrdm_wait_transition, diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index e5f0503..72df974 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -109,6 +109,8 @@ #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) #define OMAP2430_EN_USBHS_SHIFT 6 #define OMAP2430_EN_USBHS_MASK (1 << 6) +#define OMAP24XX_EN_GPMC_SHIFT 1 +#define OMAP24XX_EN_GPMC_MASK (1 << 1) /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ #define OMAP2420_ST_MMC_SHIFT 26 |
