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authorFelipe Balbi <balbi@ti.com>2014-09-08 17:54:32 -0700
committerTony Lindgren <tony@atomide.com>2014-09-11 13:03:32 -0700
commit33c7c7b7f2eb76520cd8ddcb7fe458383783e0f8 (patch)
treef382de715f31508b3cfe9c227014bc64efe5f211 /arch/arm/mach-omap2
parent176da6c766ce3d5d8c88a7afdaefcc5fd6d8afac (diff)
downloadop-kernel-dev-33c7c7b7f2eb76520cd8ddcb7fe458383783e0f8.zip
op-kernel-dev-33c7c7b7f2eb76520cd8ddcb7fe458383783e0f8.tar.gz
arm: omap: irq: define INTC_ILR0 register
this is currently used as a hardcoded 0x100 offset. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/irq.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index ae082c6..bae0329 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -41,6 +41,7 @@
#define INTC_MIR_CLEAR0 0x0088
#define INTC_MIR_SET0 0x008c
#define INTC_PENDING_IRQ0 0x0098
+#define INTC_ILR0 0x0100
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG 32
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