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authorAnand Gadiyar <gadiyar@ti.com>2010-07-26 16:34:27 -0600
committerPaul Walmsley <paul@pwsan.com>2010-07-26 16:34:27 -0600
commit25499d9353e8cc6b0cf205684b3ebc535f8b9372 (patch)
tree2313746d14fd50787286378366616e978120902c /arch/arm/mach-omap2
parentb37fa16e78d6f9790462b3181602a26b5af36260 (diff)
downloadop-kernel-dev-25499d9353e8cc6b0cf205684b3ebc535f8b9372.zip
op-kernel-dev-25499d9353e8cc6b0cf205684b3ebc535f8b9372.tar.gz
OMAP3: wait on IDLEST after enabling USBTLL fclk
We need to wait on the IDLEST bit after the clocks are enabled before attempting to access any register. Currently, the USBTLL i-clock ops uses the clkops_omap2_dflt_wait, while the USBTLL f-clock ops uses clkops_omap2_dflt. If the i-clock is enabled first, the clkops_omap2_dflt_wait is short-circuited as the companion f-clock is not enabled. This can cause a data abort if the IDLEST has not transitioned, and we try to access a USBTLL register. Since the USBTLL i-clock and f-clock could be enabled in any order, this is a bug. Fix it by changing the clkops for the f-clock. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 41b155a..c226798 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1408,7 +1408,7 @@ static struct clk ts_fck = {
static struct clk usbtll_fck = {
.name = "usbtll_fck",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll5_m2_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
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