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authorLinus Torvalds <torvalds@linux-foundation.org>2018-04-05 21:21:08 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2018-04-05 21:21:08 -0700
commit167569343fac74ec6825a3ab982f795b5880e63e (patch)
tree965adb59fbe10d9f45a7fb90cb1ec1bc18d4613c /arch/arm/mach-omap2/pm33xx-core.c
parentb240b419db5d624ce7a5a397d6f62a1a686009ec (diff)
parentcd903711fd9dce808b5cc07e509135886d962b0c (diff)
downloadop-kernel-dev-167569343fac74ec6825a3ab982f795b5880e63e.zip
op-kernel-dev-167569343fac74ec6825a3ab982f795b5880e63e.tar.gz
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann: "This release brings up a new platform based on the old ARM9 core: the Nuvoton NPCM is used as a baseboard management controller, competing with the better known ASpeed AST2xx series. Another important change is the addition of ARMv7-A based chips in mach-stm32. The older parts in this platform are ARMv7-M based microcontrollers, now they are expanding to general-purpose workloads. The other changes are the usual defconfig updates to enable additional drivers, lesser bugfixes. The largest updates as often are the ongoing OMAP cleanups, but we also have a number of changes for the older PXA and davinci platforms this time. For the Renesas shmobile/r-car platform, some new infrastructure is needed to make the watchdog work correctly. Supporting Multiprocessing on Allwinner A80 required a significant amount of new code, but is not doing anything unexpected" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits) arm: npcm: modify configuration for the NPCM7xx BMC. MAINTAINERS: update entry for ARM/berlin ARM: omap2: fix am43xx build without L2X0 ARM: davinci: da8xx: simplify CFGCHIP regmap_config ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data ARM: multi_v7_defconfig: add NXP FlexCAN IP support ARM: multi_v7_defconfig: enable thermal driver for i.MX devices ARM: multi_v7_defconfig: add RN5T618 PMIC family support ARM: multi_v7_defconfig: add NXP graphics drivers ARM: multi_v7_defconfig: add GPMI NAND controller support ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs ARM: multi_v7_defconfig: configure I2C driver built-in arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE ARM: imx: fix imx6sll-only build ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well ARM: mxs_defconfig: Re-sync defconfig ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver ARM: imx_v4_v5_defconfig: Re-sync defconfig arm64: defconfig: enable stmmac ethernet to defconfig ARM: EXYNOS: Simplify code in coupled CPU idle hot path ...
Diffstat (limited to 'arch/arm/mach-omap2/pm33xx-core.c')
-rw-r--r--arch/arm/mach-omap2/pm33xx-core.c189
1 files changed, 189 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
new file mode 100644
index 0000000..93c0b5b
--- /dev/null
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM33XX Arch Power Management Routines
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Dave Gerlach
+ */
+
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <linux/errno.h>
+#include <linux/platform_data/pm33xx.h>
+
+#include "cm33xx.h"
+#include "common.h"
+#include "control.h"
+#include "clockdomain.h"
+#include "iomap.h"
+#include "omap_hwmod.h"
+#include "pm.h"
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "soc.h"
+#include "sram.h"
+
+static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
+static struct clockdomain *gfx_l4ls_clkdm;
+static void __iomem *scu_base;
+
+static int __init am43xx_map_scu(void)
+{
+ scu_base = ioremap(scu_a9_get_base(), SZ_256);
+
+ if (!scu_base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int amx3_common_init(void)
+{
+ gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
+ per_pwrdm = pwrdm_lookup("per_pwrdm");
+ mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
+
+ if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm))
+ return -ENODEV;
+
+ (void)clkdm_for_each(omap_pm_clkdms_setup, NULL);
+
+ /* CEFUSE domain can be turned off post bootup */
+ cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
+ if (cefuse_pwrdm)
+ omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
+ else
+ pr_err("PM: Failed to get cefuse_pwrdm\n");
+
+ return 0;
+}
+
+static int am33xx_suspend_init(void)
+{
+ int ret;
+
+ gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
+
+ if (!gfx_l4ls_clkdm) {
+ pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n");
+ return -ENODEV;
+ }
+
+ ret = amx3_common_init();
+
+ return ret;
+}
+
+static int am43xx_suspend_init(void)
+{
+ int ret = 0;
+
+ ret = am43xx_map_scu();
+ if (ret) {
+ pr_err("PM: Could not ioremap SCU\n");
+ return ret;
+ }
+
+ ret = amx3_common_init();
+
+ return ret;
+}
+
+static void amx3_pre_suspend_common(void)
+{
+ omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
+}
+
+static void amx3_post_suspend_common(void)
+{
+ int status;
+ /*
+ * Because gfx_pwrdm is the only one under MPU control,
+ * comment on transition status
+ */
+ status = pwrdm_read_pwrst(gfx_pwrdm);
+ if (status != PWRDM_POWER_OFF)
+ pr_err("PM: GFX domain did not transition: %x\n", status);
+}
+
+static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long))
+{
+ int ret = 0;
+
+ amx3_pre_suspend_common();
+ ret = cpu_suspend(0, fn);
+ amx3_post_suspend_common();
+
+ /*
+ * BUG: GFX_L4LS clock domain needs to be woken up to
+ * ensure thet L4LS clock domain does not get stuck in
+ * transition. If that happens L3 module does not get
+ * disabled, thereby leading to PER power domain
+ * transition failing
+ */
+
+ clkdm_wakeup(gfx_l4ls_clkdm);
+ clkdm_sleep(gfx_l4ls_clkdm);
+
+ return ret;
+}
+
+static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long))
+{
+ int ret = 0;
+
+ amx3_pre_suspend_common();
+ scu_power_mode(scu_base, SCU_PM_POWEROFF);
+ ret = cpu_suspend(0, fn);
+ scu_power_mode(scu_base, SCU_PM_NORMAL);
+ amx3_post_suspend_common();
+
+ return ret;
+}
+
+static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
+{
+ if (soc_is_am33xx())
+ return &am33xx_pm_sram;
+ else if (soc_is_am437x())
+ return &am43xx_pm_sram;
+ else
+ return NULL;
+}
+
+static struct am33xx_pm_platform_data am33xx_ops = {
+ .init = am33xx_suspend_init,
+ .soc_suspend = am33xx_suspend,
+ .get_sram_addrs = amx3_get_sram_addrs,
+};
+
+static struct am33xx_pm_platform_data am43xx_ops = {
+ .init = am43xx_suspend_init,
+ .soc_suspend = am43xx_suspend,
+ .get_sram_addrs = amx3_get_sram_addrs,
+};
+
+static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
+{
+ if (soc_is_am33xx())
+ return &am33xx_ops;
+ else if (soc_is_am437x())
+ return &am43xx_ops;
+ else
+ return NULL;
+}
+
+void __init amx3_common_pm_init(void)
+{
+ struct am33xx_pm_platform_data *pdata;
+ struct platform_device_info devinfo;
+
+ pdata = am33xx_pm_get_pdata();
+
+ memset(&devinfo, 0, sizeof(devinfo));
+ devinfo.name = "pm33xx";
+ devinfo.data = pdata;
+ devinfo.size_data = sizeof(*pdata);
+ devinfo.id = -1;
+ platform_device_register_full(&devinfo);
+}
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