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| author | Paul Walmsley <paul@pwsan.com> | 2012-05-08 11:34:27 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-05-08 17:25:36 -0600 |
| commit | 03d830e8dcbe4e8168a85252fcb639b48342ed3c (patch) | |
| tree | 2fc25f63d1f70a5bfb1ebe31a6611439b005b904 /arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | |
| parent | 9e1b7498d79ab9076791807172d4603c7be63c1b (diff) | |
| download | op-kernel-dev-03d830e8dcbe4e8168a85252fcb639b48342ed3c.zip op-kernel-dev-03d830e8dcbe4e8168a85252fcb639b48342ed3c.tar.gz | |
ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data
Much of the HDQ1W integration data is common between multiple generations
of OMAP SoCs, so rather than make several copies, we add it once into
files which are compiled for multiple SoCs.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: NeilBrown <neilb@suse.de>
Tested-by: NeilBrown <neilb@suse.de>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index f08e442..102d76e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -2,6 +2,7 @@ * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 * * Copyright (C) 2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -12,6 +13,7 @@ #include <plat/serial.h> #include <plat/dma.h> #include <plat/common.h> +#include <plat/hdq1w.h> #include <mach/irqs.h> @@ -302,3 +304,23 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { { .irq = -1 } }; +struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x14, + .syss_offs = 0x18, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +struct omap_hwmod_class omap2_hdq1w_class = { + .name = "hdq1w", + .sysc = &omap2_hdq1w_sysc, + .reset = &omap_hdq1w_reset, +}; + +struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { + { .irq = 58, }, + { .irq = -1 } +}; + |
