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authorStrashko, Grygorii <grygorii.strashko@ti.com>2013-10-22 22:07:15 +0300
committerOlof Johansson <olof@lixom.net>2014-01-31 14:57:32 -0800
commit74ed7bdcb41d32c7628c3bd1478b076e5b1ad8a4 (patch)
tree66fd985590234a77ccbca36a9fbc06df7b968281 /arch/arm/mach-omap2/omap4-common.c
parente7651b819e90da924991d727d3c007200a18670d (diff)
downloadop-kernel-dev-74ed7bdcb41d32c7628c3bd1478b076e5b1ad8a4.zip
op-kernel-dev-74ed7bdcb41d32c7628c3bd1478b076e5b1ad8a4.tar.gz
ARM: OMAP4460: cpuidle: Extend PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD on cpuidle
The same workaround as ff999b8a0983ee15668394ed49e38d3568fc6859 "ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC ..." need to be applied not only when system is booting, but when MPUSS hits OSWR state through CPUIdle too. Without this WA the same issue is reproduced now on boards PandaES and Tablet/Blaze with SOM OMAP4460 when CONFIG_CPU_IDLE is enabled. After MPUSS has enterred OSWR and waken up: - GIC distributor became disabled forever - scheduling is not performed any more Cc: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-omap2/omap4-common.c')
-rw-r--r--arch/arm/mach-omap2/omap4-common.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index dd893ec..6cd3f37 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -127,6 +127,12 @@ void gic_dist_disable(void)
__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}
+void gic_dist_enable(void)
+{
+ if (gic_dist_base_addr)
+ __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
+}
+
bool gic_dist_disabled(void)
{
return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
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