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| author | Daniel Mack <zonque@gmail.com> | 2012-12-14 11:36:43 +0100 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2013-01-15 14:50:15 -0800 |
| commit | f50a0380897d2a5e61b251b07c50ee48fa298cfd (patch) | |
| tree | e6938333762ab86edd28f3b41ab8804a32a67d03 /arch/arm/mach-omap2/gpmc-nand.c | |
| parent | 504f3c6d73650d2afeabb86e29bfeb465f2b15df (diff) | |
| download | op-kernel-dev-f50a0380897d2a5e61b251b07c50ee48fa298cfd.zip op-kernel-dev-f50a0380897d2a5e61b251b07c50ee48fa298cfd.tar.gz | |
ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
The am33xx is capable of handling bch error correction modes, so
enable that feature in the driver.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/gpmc-nand.c')
| -rw-r--r-- | arch/arm/mach-omap2/gpmc-nand.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 3059f5e..afc1e8c 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -92,17 +92,18 @@ static int omap2_nand_gpmc_retime( static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ - if (!cpu_is_omap34xx()) { + if (!cpu_is_omap34xx() && !soc_is_am33xx()) { pr_err("BCH ecc is not supported on this CPU\n"); return 0; } /* - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. - * Other chips may be added if confirmed to work. + * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 + * and AM33xx derivates. Other chips may be added if confirmed to work. */ if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && + (!soc_is_am33xx())) { pr_err("BCH 4-bit mode is not supported on this CPU\n"); return 0; } |
