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author | Benoit Cousson <b-cousson@ti.com> | 2011-07-10 05:56:32 -0600 |
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committer | Paul Walmsley <paul@pwsan.com> | 2011-07-10 05:56:32 -0600 |
commit | 03fdefe53a3f057760751d958209f0c5507c8e40 (patch) | |
tree | 49281e94ab1367035e4029181deab683b5f07661 /arch/arm/mach-omap2/cminst44xx.c | |
parent | 27bb00b58e04e5d8442335f694f2a1b6c31b184d (diff) | |
download | op-kernel-dev-03fdefe53a3f057760751d958209f0c5507c8e40.zip op-kernel-dev-03fdefe53a3f057760751d958209f0c5507c8e40.tar.gz |
OMAP4: hwmod data: Add modulemode entry in omap_hwmod structure
Add a new field to provide the mode supported by the module.
The mode will control the way mandatory clocks are managed by the PRCM.
0 : Module is temporarily disabled by SW. OCP access to module are stalled.
Can be used to change timing parameter of GPMC module.
1 : Module is managed automatically by HW according to clock domain
transition. A clock domain sleep transition put module into idle.
A wakeup domain transition put it back into function.
If CLKTRCTRL=3, any OCP access to module is always granted.
Module clocks may be gated according to the clock domain state.
2 : Module is explicitly enabled. Interface clock (if not used for
functions) may be gated according to the clock domain state.
Functional clocks are guarantied to stay present. As long as
in this configuration, power domain sleep transition cannot happen.
Some modules will have a modulemode initialized at 1 (HWCTRL) by default.
This is the case for interconnect and simple module like GPIO, WDT, MAILBOX.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/cminst44xx.c')
0 files changed, 0 insertions, 0 deletions