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authorCharulatha V <charu@ti.com>2010-12-21 21:31:43 -0700
committerPaul Walmsley <paul@pwsan.com>2010-12-21 21:31:43 -0700
commitb183aaf7274245bb0241d81176cb6b06a3b01ca6 (patch)
tree5e26aefebe470ff6e1ca84e81ecf2ca6ace2a3d9 /arch/arm/mach-omap2/clock3xxx_data.c
parent7cffa6b888c77e9386a6b886ef10bc57aac464ec (diff)
downloadop-kernel-dev-b183aaf7274245bb0241d81176cb6b06a3b01ca6.zip
op-kernel-dev-b183aaf7274245bb0241d81176cb6b06a3b01ca6.tar.gz
OMAP3: clock: Update clock domain name for mcspi fck
Update clock3xxx_data for mcspi1-4 with appropriate clock domain name. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 27c9e14..e7a41bc 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1558,6 +1558,7 @@ static struct clk mcspi4_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.recalc = &followparent_recalc,
+ .clkdm_name = "core_l4_clkdm",
};
static struct clk mcspi3_fck = {
@@ -1567,6 +1568,7 @@ static struct clk mcspi3_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc,
+ .clkdm_name = "core_l4_clkdm",
};
static struct clk mcspi2_fck = {
@@ -1576,6 +1578,7 @@ static struct clk mcspi2_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc,
+ .clkdm_name = "core_l4_clkdm",
};
static struct clk mcspi1_fck = {
@@ -1585,6 +1588,7 @@ static struct clk mcspi1_fck = {
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.recalc = &followparent_recalc,
+ .clkdm_name = "core_l4_clkdm",
};
static struct clk uart2_fck = {
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