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authorMatt Burtch <matt@grid-net.com>2011-10-17 09:25:45 -0700
committerSascha Hauer <s.hauer@pengutronix.de>2011-10-25 11:17:44 +0200
commit590842f90984f96a3da6d8b59447dfa1d186d01e (patch)
tree488f0411e31f9ee130dbf5e72396064793c3919e /arch/arm/mach-mxs
parent6571534b600b8ca1936ff5630b9e0947f21faf16 (diff)
downloadop-kernel-dev-590842f90984f96a3da6d8b59447dfa1d186d01e.zip
op-kernel-dev-590842f90984f96a3da6d8b59447dfa1d186d01e.tar.gz
ARM: i.MX28: shift frac value in _CLK_SET_RATE
Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to reset the clock divider for the SSP0 parent clock, in this case IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but when the new frac value is written the value isn't shifted up to write the correct bit-field. This results in IO0FRAC being set to 0 and CPUFRAC being corrupted. This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0 and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1. Tested on custom i.MX28 board with SSP0 SPI driver. Signed-off-by: Matt Burtch <matt@grid-net.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mxs')
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5dcc59d..ba53227 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -349,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
- reg |= frac; \
+ reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
} \
\
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