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authorStefano Babic <sbabic@denx.de>2011-09-07 08:45:31 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2011-10-13 09:06:58 +0200
commitea42a0d058428845047206ff895e60520a7ff256 (patch)
tree25793af3f4cf89465aa65a62e02f7ee3ea14a3bc /arch/arm/mach-mxs/clock-mx28.c
parent976d167615b64e14bc1491ca51d424e2ba9a5e84 (diff)
downloadop-kernel-dev-ea42a0d058428845047206ff895e60520a7ff256.zip
op-kernel-dev-ea42a0d058428845047206ff895e60520a7ff256.tar.gz
ARM: mxs: Add initial support for DENX MX28
Added initial support for DENX M28 module and M28EVK board. Ethernet(FEC), SDHC, Display are supported. Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mxs/clock-mx28.c')
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5dcc59d..3122310 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -738,11 +738,17 @@ static int clk_misc_init(void)
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
- /* Extra fec clock setting */
- reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
- reg &= ~BM_CLKCTRL_ENET_SLEEP;
- reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
- __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+ /*
+ * Extra fec clock setting
+ * The DENX M28 uses an external clock source
+ * and the clock output must not be enabled
+ */
+ if (!machine_is_m28evk()) {
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+ reg &= ~BM_CLKCTRL_ENET_SLEEP;
+ reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+ }
/*
* 480 MHz seems too high to be ssp clock source directly,
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