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author | Dinh Nguyen <Dinh.Nguyen@freescale.com> | 2010-11-15 11:29:59 -0600 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-24 10:09:04 +0100 |
commit | c0abefd30b2c9db015df4914a95d268ecdb39b00 (patch) | |
tree | 810c6f6e8e00604a78379424a6aae2140d7fadd5 /arch/arm/mach-mx5 | |
parent | 374daa4f9019f75da1addb3f31a22df1966a5baa (diff) | |
download | op-kernel-dev-c0abefd30b2c9db015df4914a95d268ecdb39b00.zip op-kernel-dev-c0abefd30b2c9db015df4914a95d268ecdb39b00.tar.gz |
ARM: imx: Add core definitions for MX53
Add iomux, clocks, and memory map for Freescale's MX53 SoC.
Add cpu_is_mx53 function to common.h.
Add 3 more banks of gpio's to mxc_gpio_ports.
Add MX53 phys offset address.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5')
-rw-r--r-- | arch/arm/mach-mx5/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-mx5/clock-mx51-mx53.c (renamed from arch/arm/mach-mx5/clock-mx51.c) | 59 | ||||
-rw-r--r-- | arch/arm/mach-mx5/cpu.c | 43 | ||||
-rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-mx5/devices.c | 27 | ||||
-rw-r--r-- | arch/arm/mach-mx5/mm.c | 17 |
6 files changed, 129 insertions, 25 deletions
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 462f177..026cd85 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,7 +3,7 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51.o devices.o +obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 8ac36d8..ca4f9d5 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -33,6 +33,7 @@ static struct clk pll1_main_clk; static struct clk pll1_sw_clk; static struct clk pll2_sw_clk; static struct clk pll3_sw_clk; +static struct clk mx53_pll4_sw_clk; static struct clk lp_apm_clk; static struct clk periph_apm_clk; static struct clk ahb_clk; @@ -131,6 +132,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return MX51_DPLL2_BASE; else if (pll == &pll3_sw_clk) return MX51_DPLL3_BASE; + else if (pll == &mx53_pll4_sw_clk) + return MX53_DPLL4_BASE; else BUG(); @@ -514,7 +517,10 @@ static int _clk_max_enable(struct clk *clk) /* Handshake with MAX when LPM is entered. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -528,7 +534,10 @@ static void _clk_max_disable(struct clk *clk) /* No Handshake with MAX when LPM is entered as its disabled. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -739,6 +748,14 @@ static struct clk pll3_sw_clk = { .disable = _clk_pll_disable, }; +/* PLL4 SW supplies to LVDS Display Bridge(LDB) */ +static struct clk mx53_pll4_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + /* Low-power Audio Playback Mode clock */ static struct clk lp_apm_clk = { .parent = &osc_clk, @@ -1053,7 +1070,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) @@ -1084,6 +1101,14 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) }; +static struct clk_lookup mx53_lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) +}; + static void clk_tree_init(void) { u32 reg; @@ -1114,8 +1139,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, ckih2_reference = ckih2; oscillator_reference = osc; - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); + for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) + clkdev_add(&mx51_lookups[i]); clk_tree_init(); @@ -1138,3 +1163,27 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, MX51_MXC_INT_GPT); return 0; } + +int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) + clkdev_add(&mx53_lookups[i]); + + clk_tree_init(); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + /* System timer */ + mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), + MX53_INT_GPT); + return 0; +} diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 061ab70..8c9a29e 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -97,24 +97,31 @@ static int __init post_cpu_init(void) unsigned int reg; void __iomem *base; - if (!cpu_is_mx51()) - return 0; - - base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); - - base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); + if (cpu_is_mx51() || cpu_is_mx53()) { + if (cpu_is_mx51()) + base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); + else + base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); + + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + if (cpu_is_mx51()) + base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); + else + base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); + + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + } return 0; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c776b9a..51ff9bb 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -18,6 +18,9 @@ #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) +/*MX53*/ +#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) + /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 #define MXC_PLL_DP_CONFIG 0x04 @@ -380,7 +383,8 @@ /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 4c7be87..d926203 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -160,9 +160,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = { .irq_high = MX51_MXC_INT_GPIO4_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 }, + { + .chip.label = "gpio-4", + .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR), + .irq = MX53_INT_GPIO5_LOW, + .irq_high = MX53_INT_GPIO5_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, + { + .chip.label = "gpio-5", + .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR), + .irq = MX53_INT_GPIO6_LOW, + .irq_high = MX53_INT_GPIO6_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 + }, + { + .chip.label = "gpio-6", + .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR), + .irq = MX53_INT_GPIO7_LOW, + .irq_high = MX53_INT_GPIO7_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 + }, }; int __init imx51_register_gpios(void) { + return mxc_gpio_init(mxc_gpio_ports, 4); +} + +int __init imx53_register_gpios(void) +{ return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } + diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 01dff26..2822d0e 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -63,3 +63,20 @@ void __init mx51_init_irq(void) tzic_init_irq(tzic_virt); imx51_register_gpios(); } + +int imx53_register_gpios(void); + +void __init mx53_init_irq(void) +{ + unsigned long tzic_addr; + void __iomem *tzic_virt; + + tzic_addr = MX53_TZIC_BASE_ADDR; + + tzic_virt = ioremap(tzic_addr, SZ_16K); + if (!tzic_virt) + panic("unable to map TZIC interrupt controller\n"); + + tzic_init_irq(tzic_virt); + imx53_register_gpios(); +} |