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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2014-07-01 17:23:06 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-07-01 17:02:26 +0000 |
| commit | 0e2be4c1121ae3dc2771c4d9b99d4c39ea9577d8 (patch) | |
| tree | 3648fb3916e21b7d0fbb677d58dc20f2a63f99ef /arch/arm/mach-mvebu | |
| parent | 6509dc74c9f55ffaa558738b96c4da8b98d39571 (diff) | |
| download | op-kernel-dev-0e2be4c1121ae3dc2771c4d9b99d4c39ea9577d8.zip op-kernel-dev-0e2be4c1121ae3dc2771c4d9b99d4c39ea9577d8.tar.gz | |
ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian
The SMP boot on Armada 38x and Armada 375 Z1 is currently broken in
big-endian configurations, and this commit fixes it for both
platforms.
For Armada 375 Z1, the problem was in the
armada_375_smp_cpu1_enable_code part of the code that gets copied to
the Crypto SRAM as a work-around for an issue of the Z1 stepping. This
piece of code was not switching the CPU core to big-endian, and not
endian-swapping the value read from the Resume Address register (the
value is stored little-endian). Due to the introduction of the
conditional 'rev r1, r1' instruction, the offset between the 'ldr r0,
[pc, #4]' instruction and the value it was looking is different
between LE and BE configurations. To solve this, we instead use one
'adr' instruction followed by one 'ldr'.
For Armada 38x, the problem was simply that the CPU core was not
switched to big endian in the secondary CPU startup function.
This change was tested in LE and BE configurations on Armada 385,
Armada 375 Z1 and Armada 375 A0.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404228186-21203-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-mvebu')
| -rw-r--r-- | arch/arm/mach-mvebu/headsmp-a9.S | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S index 5925366..da5bb29 100644 --- a/arch/arm/mach-mvebu/headsmp-a9.S +++ b/arch/arm/mach-mvebu/headsmp-a9.S @@ -15,6 +15,8 @@ #include <linux/linkage.h> #include <linux/init.h> +#include <asm/assembler.h> + __CPUINIT #define CPU_RESUME_ADDR_REG 0xf10182d4 @@ -22,13 +24,18 @@ .global armada_375_smp_cpu1_enable_code_end armada_375_smp_cpu1_enable_code_start: - ldr r0, [pc, #4] +ARM_BE8(setend be) + adr r0, 1f + ldr r0, [r0] ldr r1, [r0] +ARM_BE8(rev r1, r1) mov pc, r1 +1: .word CPU_RESUME_ADDR_REG armada_375_smp_cpu1_enable_code_end: ENTRY(mvebu_cortex_a9_secondary_startup) +ARM_BE8(setend be) bl v7_invalidate_l1 b secondary_startup ENDPROC(mvebu_cortex_a9_secondary_startup) |
