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authorStephen Boyd <sboyd@codeaurora.org>2013-03-14 20:31:37 -0700
committerDavid Brown <davidb@codeaurora.org>2013-03-22 10:45:39 -0700
commit4080d2d11a2d572228c2b8d02406e997b87ba6a5 (patch)
treed0266e93b2f13c38d9ed2e4c0da947d5920d7e50 /arch/arm/mach-msm/timer.c
parentf6161aa153581da4a3867a2d1a7caf4be19b6ec9 (diff)
downloadop-kernel-dev-4080d2d11a2d572228c2b8d02406e997b87ba6a5.zip
op-kernel-dev-4080d2d11a2d572228c2b8d02406e997b87ba6a5.tar.gz
ARM: msm: Stop counting before reprogramming clockevent
If the clockevent is forcibly reprogrammed to have a different match value we mistakenly assume the timer is not ticking and program a new match value while the timer is running. Although we clear the timer before programming a new match, it's better to stop the timer before clearing it so that we're sure the proper amount of ticks are counted. Failure to do so can lead to missed ticks and system hangs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/timer.c')
-rw-r--r--arch/arm/mach-msm/timer.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 2969027..f9fd77e 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles,
{
u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
- writel_relaxed(0, event_base + TIMER_CLEAR);
+ ctrl &= ~TIMER_ENABLE_EN;
+ writel_relaxed(ctrl, event_base + TIMER_ENABLE);
+
+ writel_relaxed(ctrl, event_base + TIMER_CLEAR);
writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
return 0;
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