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| author | Jiri Kosina <jkosina@suse.cz> | 2010-08-04 15:14:38 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2010-08-04 15:14:38 +0200 |
| commit | d790d4d583aeaed9fc6f8a9f4d9f8ce6b1c15c7f (patch) | |
| tree | 854ab394486288d40fa8179cbfaf66e8bdc44b0f /arch/arm/mach-lpc32xx/include/mach/entry-macro.S | |
| parent | 73b2c7165b76b20eb1290e7efebc33cfd21db1ca (diff) | |
| parent | 3a09b1be53d23df780a0cd0e4087a05e2ca4a00c (diff) | |
| download | op-kernel-dev-d790d4d583aeaed9fc6f8a9f4d9f8ce6b1c15c7f.zip op-kernel-dev-d790d4d583aeaed9fc6f8a9f4d9f8ce6b1c15c7f.tar.gz | |
Merge branch 'master' into for-next
Diffstat (limited to 'arch/arm/mach-lpc32xx/include/mach/entry-macro.S')
| -rw-r--r-- | arch/arm/mach-lpc32xx/include/mach/entry-macro.S | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S new file mode 100644 index 0000000..870227c --- /dev/null +++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-lpc32xx/include/mach/entry-macro.S + * + * Author: Kevin Wells <kevin.wells@nxp.com> + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <mach/platform.h> + +#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + +/* + * Return IRQ number in irqnr. Also return processor Z flag status in CPSR + * as set if an interrupt is pending. + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + teq \irqstat, #0 + .endm + + .macro irq_prio_table + .endm + |
